The formation of a dense and uniform thin layer on the substrates is crucial for the fabrication of high-performance perovskite solar cells (PSCs) containing formamidinium with multiple cations and mixed halide anions. The concentration of defect states, which reduce a cell’s performance by decreasing the open-circuit voltage and short-circuit current density, needs to be as low as possible. We show that the introduction of additional iodide ions into the organic cation solution, which are used to form the perovskite layers through an intramolecular exchanging process, decreases the concentration of deep-level defects. The defect-engineered thin perovskite layers enable the fabrication of PSCs with a certified power conversion efficiency of 22.1% in small cells and 19.7% in 1-square-centimeter cells.

Iodide management in formamidinium-lead-halide–based perovskite layers for efficient solar cells

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

http://www.nanoscience.gatech.edu/paper/2012/12_NE_04.pdf

Flexible triboelectric generator

In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

Metal–Oxide RRAM

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures

The fabrication of controlled nanostructures such as quantum dots, nanotubes, nanowires, and nanopillars has progressed rapidly over the past 10 years. However, both bottom-up and top-down methods to integrate the nanostructures are met with several challenges. For practical applications with the high level of the integration, an approach that can fabricate the required structures locally is desirable. In addition, the electrical signal to construct and control the nanostructures can provide significant advantages toward the stability and ordering. Through experiments on the negative resistance switching phenomenon in Pt-NiO-Pt structures, we have fabricated nanofilament channels that can be electrically connected or disconnected. Various analyses indicate that the nanofilaments are made of nickel and are formed at the grain boundaries. The scaling behaviors of the nickel nanofilaments were closely examined, with respect to the switching time, power, and resistance. In particular, the 100 nm x 100 nm cell was switchable on the nanosecond scale, making them ideal for the basis for high-speed, high-density, nonvolatile memory applications.

Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory.

For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process With 10nm diameter nanowire, saturation currents through twin nanowires of 264 mA/mum, 111 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

[*] Prof. S.-W. Kim, H.-K. Park, J.-S. Seo School of Advanced Materials Science and Engineering SKKU Advanced Institute of Nanotechnology (SAINT) Center for Human Interface Nanotechnology (HINT) Sungkyunkwan University Suwon, 440-746 (Republic of Korea) E-mail: kimsw1@skku.edu Dr. J.-Y. Choi, Dr. D. Choi, Dr. W. M. Choi, H.-J. Shin, Dr. J. Park, S.-M. Yoon, Dr. S. Y. Lee, Dr. J. M. Kim Samsung Advanced Institute of Technology Yongin, Gyeonggi, 446-712 (Republic of Korea) E-mail: jaeyoung88.choi@samsung.com M.-Y. Choi School of Advanced Materials and System Engineering Kumoh National Institute of Technology Gumi, Gyeongbuk, 730-701 (Republic of Korea)

Fully Rollable Transparent Nanogenerators Based on Graphene Electrodes

We have successfully integrated a 2-stack 8times8 array 1D- lR (one diode-one resistor) structure with 0.5 mumtimes0.5 mum cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuOx/n-InZnOx heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiOx/n-TiOx oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8times8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuOx/n-IZOx diodes was over 104A/cm2, and the operation voltage for the storage node with diode attached was around 3 V.

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

The impact of gate metals on the threshold voltage (VTH) and the gate current of p-GaN gate high-electron-mobility transistors (HEMTs) is investigated by fabricating p-GaN gate HEMTs with different work function gate metals-Ni and W. p-GaN gate HEMTs incorporate a p-GaN layer under the gate electrode as the gate stack on top of the AlGaN/GaN layer. In comparison to the Ni-gate p-GaN HEMTs, the W-gate p-GaN HEMTs showed a higher VTH of 3.0 V and a lower gate current of 0.02 mA/mm at a gate bias of 10 V. Based on TCAD device simulations, we revealed that these high VTH and low gate current are attributed to the low gate metal work function and the high Schottky barrier between the p-GaN and the W gate metal.

Jong-Bong Park

Papers

Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory.

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Fully Rollable Transparent Nanogenerators Based on Graphene Electrodes

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

p-GaN Gate HEMTs With Tungsten Gate Metal for High Threshold Voltage and Low Gate Current