Jong-Tae Park

Bio: Jong-Tae Park is an academic researcher from Incheon National University. The author has contributed to research in topics: Threshold voltage & Transistor. The author has an hindex of 15, co-authored 100 publications receiving 1506 citations. Previous affiliations of Jong-Tae Park include Kwangwoon University.

Multiple-gate SOI MOSFETs: device design guidelines

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

Pi-Gate SOI MOSFET

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET.

Device design guidelines for nano-scale MuGFETs

Abstract: The short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as DIBL, subthreshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. This number ranges from 2 for a double-gate device to 4 in a gate-all-around transistor. The equivalent gate number can be used in general equations to predict the absence or presence of short-channel effects. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

RF performance degradation in nMOS transistors due to hot carrier effects

Abstract: This paper reports the hot electron induced RF performance degradation in multifinger gate nMOS transistors within the general framework of the degradation mechanism. The RF performance degradation of hot-carrier stressed nMOS transistors can be explained by the transconductance degradation, which resulted from the interface state generation. It has been found that the RF performance degradation, especially minimum noise figure degradation, is more significant than dc performance degradation. From the experimental correlation between RF and dc performance degradation, RF performance degradation can be predicted just by the measurement of dc performance degradation or the initial substrate current. From our experimental results, hot electron induced RF performance degradation should be taken into consideration in the design of the CMOS RF integrated circuits.

SOI dual-gate ISFET with variable oxide capacitance and channel thickness

Abstract: A dual-gate (DG) ion sensitive field effect transistor (ISFET) using capacitance coupling effect has recently been proposed to overcome the Nernst limitation as 59 mV/pH. In this study, we focus on the analysis of sensing characteristics by various oxide capacitances and channel thickness using intensive measurement on conventional fully depleted (FD) silicon-on-insulator (SOI) based DG ISFET. The enlarged oxide capacitance and reductive channel thickness enhance the capacitive coupling effect and increase sensitivity of DG ISFET. And also, the thin channel thickness reduced the leakage current in the DG operation. These will be very promising techniques for high performance biosensor application.

Advances of flexible pressure sensors toward artificial intelligence and health care applications

Abstract: By virtue of their wide applications in personal electronic devices and industrial monitoring, pressure sensors are attractive candidates for promoting the advancement of science and technology in modern society. Flexible pressure sensors based on organic materials, which combine unique advantages of flexibility and low-cost, have emerged as a highly active field due to their promising applications in artificial intelligence systems and wearable health care devices. In this review, we focus on the fundamentals of flexible pressure sensors, and subsequently on several critical concepts for the exploration of functional materials and optimization of sensing devices toward practical applications. Perspectives on self-powered, transparent and implantable pressure sensing devices are also examined to highlight the development directions in this exciting research field.

Multiple-gate SOI MOSFETs

Abstract: In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Abstract: For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Ultrawide-Bandgap Semiconductors: Research Opportunities and Challenges

Abstract: J. Y. Tsao,* S. Chowdhury, M. A. Hollis,* D. Jena, N. M. Johnson, K. A. Jones, R. J. Kaplar,* S. Rajan, C. G. Van de Walle, E. Bellotti, C. L. Chua, R. Collazo, M. E. Coltrin, J. A. Cooper, K. R. Evans, S. Graham, T. A. Grotjohn, E. R. Heller, M. Higashiwaki, M. S. Islam, P. W. Juodawlkis, M. A. Khan, A. D. Koehler, J. H. Leach, U. K. Mishra, R. J. Nemanich, R. C. N. Pilawa-Podgurski, J. B. Shealy, Z. Sitar, M. J. Tadjer, A. F. Witulski, M. Wraback, and J. A. Simmons