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Author

Jongwook Jeon

Other affiliations: Seoul National University, Samsung
Bio: Jongwook Jeon is an academic researcher from Konkuk University. The author has contributed to research in topics: Noise figure & Flicker noise. The author has an hindex of 11, co-authored 85 publications receiving 490 citations. Previous affiliations of Jongwook Jeon include Seoul National University & Samsung.


Papers
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Proceedings ArticleDOI
10 Dec 2000
TL;DR: Al/sub 2/O/sub 3/ (EOT=227 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices as discussed by the authors.
Abstract: Al/sub 2/O/sub 3/ (EOT=227 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge

67 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed that gm 2/ID, which has been used as the figure of merit (FoM) of MOSFETs for analog amplifiers, can also be used as a FoM for low-noise amplifier (LNA) performance.
Abstract: In this letter, it is proposed that gm 2/ID, which has been used as the figure of merit (FoM) of MOSFETs for analog amplifiers, can also be used as the RF MOSFET FoM for optimizing low-noise amplifier (LNA) performance. From a simple small-signal equivalent circuit, signal gain, noise figure, and power consumption equations are derived analytically and verified with the measurement results of the fabricated LNA. The proposed gm 2/ID predicts the optimal bias point for the maximum LNA performance.

40 citations

Journal ArticleDOI
TL;DR: An accurate and efficient machine learning (ML) approach which predicts variations in key electrical parameters using process variations (PVs) from ultrascaled gate-all-around (GAA) vertical FET (VFET) devices with the same degree of accuracy, as well as improved efficiency compared to a 3-D stochastic TCAD simulation.
Abstract: In this brief, we present an accurate and efficient machine learning (ML) approach which predicts variations in key electrical parameters using process variations (PVs) from ultrascaled gate-all-around (GAA) vertical FET (VFET) devices. The 3-D stochastic TCAD simulation is the most powerful tool for analyzing PVs, but for ultrascaled devices, the computation cost is too high because this method requires simultaneous analysis of various factors. The proposed ML approach is a new method which predicts the effects of the variability sources of ultrascaled devices. It also shows the same degree of accuracy, as well as improved efficiency compared to a 3-D stochastic TCAD simulation. An artificial neural network (ANN)-based ML algorithm can make multi-input -multi-output (MIMO) predictions very effectively and uses an internal algorithm structure that is improved relative to existing techniques to capture the effects of PVs accurately. This algorithm incurs approximately 16% of the computation cost by predicting the effects of process variability sources with less than 1% error compared to a 3-D stochastic TCAD simulation.

33 citations

Journal ArticleDOI
TL;DR: In this article, a 17/24 GHz dual-band CMOS low-noise amplifier (LNA) for ISM-band application is presented, which employs a positive feedback transmission-line-based LCladder network to obtain dualband operation and reduce power consumption.
Abstract: A 17/24 GHz dual-band CMOS low-noise amplifier (LNA) for ISM-band application is presented. The proposed LNA employs a positive feedback transmission-line-based LC-ladder network to obtain dual-band operation and reduce power consumption. For low cost, the LNA has been fabricated using a 0.18 mum mixed-signal CMOS process. The implemented LNA shows gains of 9.2 and 12 dB, and noise figures (NF) of 5.7 and 6.4 dB at 18 and 24.5 GHz, respectively. The proposed LNA exhibits 8 mW power consumption from a 0.8 V supply and the active chip area, including pad, is about 720 times 460 mum 2 .

29 citations

Journal ArticleDOI
TL;DR: In this article, an analytical channel thermal noise model for short channel MOSFETs is derived, which takes into account the channel length modulation, velocity saturation, and carrier heating effects in the gradual channel region.
Abstract: In this work, an analytical channel thermal noise model for short channel MOSFETs is derived. The transfer function of the noise was derived by following the Tsividis’ method. The proposed model takes into account the channel length modulation, velocity saturation, and carrier heating effects in the gradual channel region. Modeling results show good agreements with the measured noise data.

29 citations


Cited by
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01 Jan 2003
TL;DR: In this article, a survey of 1/f noise in homogeneous semiconductor samples is presented, where a distinction is made between mobility noise and number noise, and it is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/.
Abstract: This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

523 citations

Journal ArticleDOI
TL;DR: In this paper, the authors review various causes of threshold voltage instability in high/spl kappa/ gate dielectric stacks, including charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects.
Abstract: Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

208 citations

Book ChapterDOI
01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

207 citations

Patent
30 Aug 2004
TL;DR: In this article, an asymmetrical low tunnel barrier intergate insulator is proposed for programmable array type logic and/or memory devices with atomic layer deposition, which includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2 and Nb2O2.
Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

204 citations