Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

2005년 대한 생화학·분자생물학회 하계학술대회를 다녀와서

The authors present a software-oriented approach to hardware-software partitioning which avoids restrictions on the software semantics as well as an iterative partitioning process based on hardware extraction controlled by a cost function. This process is used in Cosyma, an experimental cosynthesis system for embedded controllers. As an example, the extraction of coprocessors for loops is demonstrated. Results are presented for several benchmark designs. >

Hardware-software cosynthesis for microcontrollers

The reliance on multi/many-core systems to satisfy the high performance requirement of complex embedded software applications is increasing. This necessitates the need to realize efficient mapping methodologies for such complex computing platforms. This paper provides an extensive survey and categorization of state-of-the-art mapping methodologies and highlights the emerging trends for multi/many-core systems. The methodologies aim at optimizing system's resource usage, performance, power consumption, temperature distribution and reliability for varying application models. The methodologies perform design-time and run-time optimization for static and dynamic workload scenarios, respectively. These optimizations are necessary to fulfill the end-user demands. Comparison of the methodologies based on their optimization aim has been provided. The trend followed by the methodologies and open research challenges have also been discussed.

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Mapping on multi/many-core systems: survey of current and emerging trends

High performance approximate adders typically comprise of multiple smaller sub-adders, carry prediction units and error correction units In this paper, we present a low-latency generic accuracy configurable adder to support variable approximation modes It provides a higher number of potential configurations compared to state-of-the-art, thus enabling a high degree of design flexibility and trade-off between performance and output quality An error correction unit is integrated to provide accurate results for cases where high accuracy is required Furthermore, an associated scheme for error probability estimation allows convenient comparison of different approximate adder configurations without requiring the need to numerically simulate the adder Our experimental results validate the developed error model and also the lower latency of our generic accuracy configurable adder over state-of-the-art approximate adders For functional verification and prototyping, we have used a Xilinx Virtex-6 FPGA Our adder model and synthesizable RTL are made open-source

A low latency generic accuracy configurable adder

As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts More and more processor cores and large, reusable components are being integrated on a single silicon die but reuse of the communication infrastructure has been difficult Buses and point to point connections, that have been the main means to connect components on a chip today, will not result in a scalable platform architecture for the billion transistor chip era Buses can cost efficiently connect a few tens of components Point to point connections between communication partners is practical for even fewer components As more and more components are integrated on a single silicon die, performance bottlenecks of long, global wires preclude reuse of buses Therefore, scalable on-chip communication infrastructure is playing an increasingly dominant role in system-on-chip designs With the super-abundance of cheap, function-specific IP cores, design effort will focus on the weakest link: efficient on-chip communication Future on-chip communication infrastructure will overcome the limits of bus-based systems by providing higher bandwidth, higher flexibility and by solving the clock skew problem on large chips It may, however, present new problems: higher power consumption of the communication infrastructure and harder-to-predict performance patterns Solutions to these problems may result in a complete overhaul of SOC design methodologies into a communication-centric design style The envisioning of upcoming problems and possible benefits has led to intensified research in the field of what is called NoCs: Networks on Chips The term NoCs is used in a broad meaning, encompassing the hardware communication infrastructure, the middleware and operating system communication services, and a design methodology and tools to map applications onto a network on chip This paper discusses trends in system-on-chip designs, critiques problems and opportunities of the NoC paradigm, summarizes research activities, and outlines several directions for future research

On-chip networks: a scalable, communication-centric embedded system design paradigm

Design-time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. This drives the development of run-time adaptive systems. To the best of our knowledge, we are presenting the first scheme for a runtime application mapping in a distributed manner using agents targeting for adaptive NoC-based heterogeneous multi-processor systems. Our approach reduces the overall traffic produced to collect the current state of the system (monitoring-traffic), needed for runtime mapping, compared to a centralized mapping scheme. In our experiment, we obtain 10.7 times lower monitoring traffic compared to the centralized mapping scheme proposed in [8] for a 64 times 64 NoC. Our proposed scheme also requires less execution cycles compared to a non-clustered centralized approach. We achieve on an average 7.1 times lower computational effort for the mapping algorithm compared to the simple nearest-neighbor (NN) heuristics proposed in (E. Carvalho et al., 2007) in a 64 times 32 NoC. We demonstrate the advantage of our scheme by means of a robot application and a set of multimedia applications and compare it to the state-of-the-art run-time mapping schemes proposed in ((E. Carvalho et al., 2007), (C.-L. Chou and R. Marculescu, 2007),(L. Smit et al., 2004)).

Jorg Henkel

Papers

Hardware-software cosynthesis for microcontrollers

Mapping on multi/many-core systems: survey of current and emerging trends

A low latency generic accuracy configurable adder

On-chip networks: a scalable, communication-centric embedded system design paradigm

ADAM: run-time agent-based distributed application mapping for on-chip communication