Jorge Guilherme

Bio: Jorge Guilherme is an academic researcher from Instituto Politécnico Nacional. The author has contributed to research in topics: Integrated circuit design & CMOS. The author has an hindex of 11, co-authored 66 publications receiving 537 citations. Previous affiliations of Jorge Guilherme include Instituto Superior Técnico & Technical University of Lisbon.

Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques

Abstract: The microelectronics market trends present an ever-increasing level of complexity with special emphasis on the production of complex mixed-signal systems-on-chip. Strict economic and design pressures have driven the development of new methods to automate the analog design process. However, and despite some significant research efforts, the essential act of design at the transistor level is still performed by the trial and error interaction between the designer and the simulator. This book presents a new design automation methodology based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.

AIDA: Automated analog IC design flow from circuit level to layout

Abstract: This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to a physical layout description. AIDA results from the integration of two in-house tools, namely, GENOM-POF and LAYGEN II. GENOM-POF performs fully automated circuit-level synthesis implemented with a multi-objective multi-constraint optimization approach, which addresses robust design requirements by considering Corners analysis together with an electrical simulator as the evaluation engine. LAYGEN II implements a DRC proved fully automated layout generation based on a sized circuit-level description and high level layout guidelines, described in a technology independent abstract layout template. The expert knowledge is used by LAYGEN II to guide the evolutionary optimization kernels during the automatic layout generation. Moreover, evolutionary computation techniques are extensively used, at both circuit-level and physical-level, as tool to solve design optimization problems. Finally, AIDA environment is demonstrated for the IC design of a classical circuit-level topology and state-of-the-art technology, and validated by industrial simulators and analysis tools, such as, HSPICE® and CALIBRE®.

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

Abstract: A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.

An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits

Abstract: The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently for the optimization problems involving the evaluations of black-box functions with high computational cost in either objective functions or constraints. In this paper, we propose a weighted expected improvement-based Bayesian optimization approach for automated analog circuit sizing. Gaussian processes (GP) are used as the online surrogate models for circuit performances. Expected improvement is selected as the acquisition function to balance the exploration and exploitation during the optimization procedure. The expected improvement is weighted by the probability of satisfying the constraints. In this paper, we propose a complete Bayesian optimization framework for the optimization of analog circuits with constraints for the first time. The existing GP model-based optimization methods for analog circuits take the GP models as either offline models or as assistance for the evolutionary algorithms. We also extend the Bayesian optimization algorithm to handle multi-objective optimization problems. Compared with the state-of-the-art approaches listed in this paper, the proposed Bayesian optimization method achieves better optimization results with significantly less number of simulations.

A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC

Abstract: This paper describes a neurostimulation IC for use in advanced closed-loop neurostimulation applications, such as deep brain stimulation (DBS) for treatment and research of neurological disorders including Parkinson's disease. This system senses and filters neural activity with eight pre-amplifiers, a 200 kS/s 8-bit log ADC and digital filters and incorporates 64 programmable current-stimulation channels. The entire device, implemented in 0.18 μm CMOS, occupies 2.7 mm2 and consumes 89 μW in normal operation mode and 271 μW in configuration mode from a 1.8 V supply.

Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques

Abstract: In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and response-surface-based yield optimization methods face challenges in accuracy. Monte-Carlo (MC) simulation is general and accurate for yield estimation, but its efficiency is not high enough to make MC-based analog yield optimization, which requires many yield estimations, practical. In this paper, techniques inspired by computational intelligence are used to speed up yield optimization without sacrificing accuracy. A new sampling-based yield optimization approach, which determines the device sizes to optimize yield, is presented, called the ordinal optimization (OO)-based random-scale differential evolution (ORDE) algorithm. By proposing a two-stage estimation flow and introducing the OO technique in the first stage, sufficient samples are allocated to promising solutions, and repeated MC simulations of non-critical solutions are avoided. By the proposed evolutionary algorithm that uses differential evolution for global search and a random-scale mutation operator for fine tunings, the convergence speed of the yield optimization can be enhanced significantly. With the same accuracy, the resulting ORDE algorithm can achieve approximately a tenfold improvement in computational effort compared to an improved MC-based yield optimization algorithm integrating the infeasible sampling and Latin-hypercube sampling techniques. Furthermore, ORDE is extended from plain yield optimization to process-variation-aware single-objective circuit sizing.