J
Jose Cruz-Albrecht
Researcher at HRL Laboratories
Publications - 49
Citations - 1589
Jose Cruz-Albrecht is an academic researcher from HRL Laboratories. The author has contributed to research in topics: Neuromorphic engineering & Signal. The author has an hindex of 15, co-authored 49 publications receiving 1455 citations. Previous affiliations of Jose Cruz-Albrecht include University of Pittsburgh.
Papers
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Journal ArticleDOI
A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications
Kuk-Hwan Kim,Siddharth Gaba,Dana C. Wheeler,Jose Cruz-Albrecht,Tahir Hussain,Narayan Srinivasa,Wei Lu +6 more
TL;DR: A high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the Memristor element.
Journal ArticleDOI
Energy-Efficient Neuron, Synapse and STDP Integrated Circuits
TL;DR: Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented that include a spike timing dependent plasticity (STDP) learning rule circuit and demonstrate proper operation.
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A scalable neural chip with synaptic electronics using CMOS integrated memristors
TL;DR: The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented and circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior are provided.
Patent
Down-converter and up-converter for time-encoded signals
Jose Cruz-Albrecht,Peter Petre +1 more
TL;DR: In this paper, an apparatus and methods that can convert frequencies of time-encoded signals is described. But the proposed method is limited to the radio frequency range and requires the use of a time encoder and a bandpass filter.
Journal ArticleDOI
Programming Time-Multiplexed Reconfigurable Hardware Using a Scalable Neuromorphic Compiler
TL;DR: A programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM), which enables the proposed architecture to address scalability and connectivity using traditional CMOS hardware.