Joselyn Torres

Bio: Joselyn Torres is an academic researcher from Texas A&M University. The author has contributed to research in topics: Voltage regulator & Low-dropout regulator. The author has an hindex of 8, co-authored 11 publications receiving 451 citations. Previous affiliations of Joselyn Torres include Silicon Labs.

High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

Abstract: A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 ?m CMOS technology and achieves a PSR better than - 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 ?A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz.

Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison

Abstract: Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This paper compares CL-LDOs in a unified matter. We designed, fabricated, and tested five illustrative CL-LDO regulator topologies under common design conditions using 0.6?m CMOS technology. We compare the architectures in terms of (1) line/load regulation, (2) power supply rejection, (3) line/load transient, (4) total on-chip compensation capacitance, (5) noise, and (6) quiescent power consumption. Insights on what optimal topology to choose to meet particular LDO specifications are provided.

A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads

Abstract: This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18- $\mu \text{m}$ CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency.

A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

Abstract: This paper presents an internally compensated capacitor-less low dropout regulator (CL-LDO) with bulk-driven feed-forward supply noise cancellation and adaptive compensation for fast settling time ( TS ). A feed-forward path from the CL-LDO's supply input to the output is implemented to increase power supply rejection (PSR) from mid-range frequencies to up to 5 MHz. The CL-LDO achieves a −90 dB low frequency and –64 dB PSR at 1 MHz for 50 mA of load current ( IL ). A transconductance amplifier with adaptive Miller compensation based on IL sense is used to increase the unity-gain frequency by 40× at heavy loads. The CL-LDO achieves a 0.3 mV/V line regulation, 10 μ V/mA load regulation, 300 ns of TS , and 0.16 ps figure of merit, which is 7.5× better than current state-of-the-art CL-LDOs. The CL-LDO was fabricated in CMOS 130 nm technology, consumes IQ of 42 μ A, has a dropout voltage ( V DO) of 200 mV for IL of 50 mA, and occupies an active area of 0.0046 mm2.

A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than −56dB up to 10MHz using a feedforward ripple-cancellation technique

Abstract: Low drop-out (LDO) linear regulators have become a key building block in portable communication systems for power management ICs. The LDO usually comes after a switching DC-DC converter to reduce the output ripples and provide a regulated voltage source for noise-sensitive blocks. For a higher level of integration, there is a need to increase the operating frequency of the switching converters [1]. This necessitates a subsequent LDO regulator with high ripple rejection at frequencies up to several MHz. These LDO regulators should also provide a low drop-out voltage to cope with the low supply voltage of the state-of-the-art CMOS technologies. In addition, due to the feedback nature of the system, the LDO should be stable for a wide range of supply currents while consuming a very low quiescent current.

High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

Abstract: A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 ?m CMOS technology and achieves a PSR better than - 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 ?A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz.

External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4–4 MHz Range

Abstract: This paper presents design techniques for a high power supply rejection (PSR) low drop-out (LDO) regulator. A bulky external capacitor is avoided to make the LDO suitable for system-on-chip (SoC) applications while maintaining the capability to reduce high-frequency supply noise. The paths of the power supply noise to the LDO output are analyzed, and a power supply noise cancellation circuit is developed. The PSR performance is improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. The effectiveness of the PSR enhancement technique is experimentally verified with an LDO that was fabricated in a 0.18 μm CMOS technology with a power supply of 1.8 V. The active core chip area is 0.14 mm2, and the entire proposed LDO consumes 80 μA of quiescent current during operation mode and 55 μA of quiescent current in standby mode. It has a drop-out voltage of 200 mV when delivering 50 mA to the load. The measured PSR is better than -56 dB up to 4 MHz when delivering a current of 50 mA. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively.

Multiinput DC–DC converters in renewable energy applications – An overview

Abstract: Power electronics DC–DC converters are being widely used in various applications like hybrid energy systems, hybrid vehicles, aerospace, satellite applications and portable electronics devices. In the recent past, a lot of research and development has been carried out to enhance the reliability, efficiency, modularity and cost effectiveness of these converters. A number of new topologies have been proposed and new characteristics of power conversion have been defined. DC–DC converters have made a successful transition from single input–single output to multiinput–multioutput converters. These converters are now able to interface different level inputs and combine their advantages to feed the different level of outputs. Research is continued to bring down the cost and reduce the number of components while keeping the continuous improvement in the areas like reliability and efficiency of the overall system. The study of different multiinput DC–DC converter topologies suggests that there is no single topology which can handle the entire goals of cost, reliability, flexibility, efficiency and modularity single handed. This paper presents some of the recent trends in the development of multiinput and multioutput DC–DC converters. Methods to synthesize multiinput converters, their operational principles, merits and demerits are studied.

A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection

Abstract: A fully-integrated low-dropout regulator (LDO) with fast transient response and full spectrum power supply rejection (PSR) is proposed to provide a clean supply for noise-sensitive building blocks in wideband communication systems. With the proposed point-of-load LDO, chip-level high-frequency glitches are well attenuated, consequently the system performance is improved. A tri-loop LDO architecture is proposed and verified in a 65 nm CMOS process. In comparison to other fully-integrated designs, the output pole is set to be the dominant pole, and the internal poles are pushed to higher frequencies with only 50 μA of total quiescent current. For a 1.2 V input voltage and 1 V output voltage, the measured undershoot and overshoot is only 43 mV and 82 mV, respectively, for load transient of 0 μA to 10 mA within edge times of 200 ps. It achieves a transient response time of 1.15 ns and the figure-of-merit (FOM) of 5.74 ps. PSR is measured to be better than -12 dB over the whole spectrum (DC to 20 GHz tested). The prototype chip measures 260×90 μm 2 , including 140 pF of stacked on-chip capacitors.