scispace - formally typeset
Search or ask a question
Author

Joshua Gess

Bio: Joshua Gess is an academic researcher from Oregon State University. The author has contributed to research in topics: Boiling & Heat transfer. The author has an hindex of 6, co-authored 19 publications receiving 73 citations. Previous affiliations of Joshua Gess include Auburn University & University of Alabama.

Papers
More filters
Journal ArticleDOI
TL;DR: In this paper, the authors look at the entire cooling approach from the chip level all the way to the plenum level, and propose a solution with dimensions of $150~{rm mm} \times 300~{\rm mm] \times 38$ mm ( $H \times L \times W$ ).
Abstract: As the demand grows for electronics to become faster and more compact, the expectation for tomorrow’s data center is no different. Like many of the current high performance data center installations, design considerations on all scales must be taken into account. The proposed solution does just this by looking at the entire cooling approach from the chip level all the way to the plenum level. The solution’s enclosure, where all the heated elements are immersed in either FC-72 or Novec 649, has dimensions of $150~{\rm mm} \times 300~{\rm mm} \times 38$ mm ( $H \times L \times W$ ). The design is versatile allowing for either flow or pool boiling heat transfer. Under pool boiling conditions, heat transfer coefficients as high as 11.5 kW/ $\text{m}^{2}\,\cdot \,\text{K}$ were achieved with surface enhancements and maximum power dissipations as high as 320 W were yielded as chip temperatures were roughly 58 °C, well below typical operating conditions. With the introduction of dielectric fluid flow within the enclosure, maximum power dissipations achieved increased substantially, reaching 605 W, which corresponds to a volumetric power dissipation of 0.354 W/cm3.

24 citations

Proceedings ArticleDOI
09 Mar 2014
TL;DR: In this article, a pool boiling study was conducted on an array of four bare die using two different dielectric fluids; namely Novec 649 and HFE 7100, both with low global warming potential (GWP).
Abstract: Immersion cooling is making a resurgence for use in server applications driven by an increase in chip densities and the need for reduction in overall data center power usage. This paper focuses on pool boiling characteristics from an array of heaters which simulate electronic chips on a vertically-oriented printed circuit board. A pool boiling study was conducted on an array of four bare die using two different dielectric fluids; namely Novec 649 and HFE 7100, both with low global warming potential (GWP). Tests were conducted at two die spacings; 25mm and 10mm under two different pool conditions: saturated and 15°C subcooled representing a start-up transient. Data were collected for increasing and decreasing heat flux cycles. The flux dissipated was found to be 14.6 W/cm 2 and 14.2 W/cm 2 with Novec 649 and HFE 7100 respectively for the test board with 10mm die spacings under subcooled conditions. These values are recorded at self-imposed maximum surface temperatures that ensured operation well below the critical heat flux. These flux values are quite high especially since they are attained without the need to modify the surface or add heat sinks. In an effort to increase thermal performance, tests were also conducted on dies spaced 25mm apart augmented with two different enhanced heat sinks featuring microporous and microfinned surfaces. Enhanced heat sinks performed better than bare die and the flux dissipated was found to be 18.87 W/cm 2 and 18.31 W/cm 2 using Novec 649 and HFE 7100 respectively under subcooled conditions. Additionally, these values were achieved at surface temperatures 15°C lower than the surface temperatures recorded by the bare dies for dissipating the same amount of heat. High speed images were obtained to provide a better understanding of nucleation characteristics.

14 citations

Proceedings ArticleDOI
27 May 2014
TL;DR: Work has been completed on a small form factor, modular, high performance liquid immersion cooled server model with heat dissipations of over 700 Watts, achieved by the integration of enhanced surfaces affixed to the bare silicon die to promote increased boiling performance.
Abstract: The impact of increasing power consumption trends on a global economy with limited resources to sustain them cannot be understated. As worldwide communication requirements expand, data centers will need to be designed more efficiently to not only keep operation costs down for a business' bottom line, but also to be mindful of the world's power availability and resource supply. Therefore, the importance of designing data centers efficiently, but also compactly grows in step with society's power demands. To integrate into this new smarter data center, work has been completed on a small form factor, modular, high performance liquid immersion cooled server model with heat dissipations of over 700 Watts. These high power dissipations were achieved by the integration of enhanced surfaces affixed to the bare silicon die to promote increased boiling performance. The two surfaces tested were a sintered copper microporous heat sink and one that contained a dense array of microscale fins.

11 citations

Proceedings ArticleDOI
09 Mar 2014
TL;DR: In this article, a small form factor, high input power solution that involves no surface modifications, i.e. bare silicon die, is presented to meet the cooling demands of next generation servers.
Abstract: As the demand for power consumption increases with an expanding global economy, the need for innovative solutions to meet the cooling demands of next generation servers looms large. Particular attention must be paid to ensuring that cooling mechanisms employed are not only efficient from a power consumption perspective, but tightly packed to avoid needlessly expansive server rooms resulting in increased construction costs and energy waste from cooling superfluous spaces. With these concerns in mind, a small form factor, high input power solution is presented that involves no surface modifications, i.e. bare silicon die. In this 150 mm × 300 mm × 38 mm (H × L × W) space, two-phase heat transfer results in roughly 400 Watts rejected from the four-die arrangement and at a level well below the Critical Heat Flux.

10 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: In this article, the state-of-the-art of multi-level thermal management techniques for both air- and liquid-cooled data centers is reviewed. But the main focus is on the sources of inefficiencies and the improvement methods with their configuration features and performances at each level.

272 citations

Journal ArticleDOI
TL;DR: In this paper, the authors compared the heat transfer characteristics of several cooling technologies with potential application in the server electronics industry and concluded that some form of liquid cooling is necessary in high performance computing applications.

164 citations

Journal ArticleDOI
TL;DR: This review looks at various thermal management approaches that have been demonstrated in electronic systems, with a specific emphasis on the challenges and needs for next-generation high-voltage power electronics.
Abstract: A host of high-voltage-capable electronic packaging approaches have emerged in recent years for usage in next-generation power electronics. In this article, the focus is on the challenge of managing the thermal characteristics in these cutting edge packaging options, where power densities are exceeding 25 kW/L. Utilizing wide bandgap semiconductors like SiC and GaN can help reduce the thermal inefficiencies associated with conduction losses by using high-frequency switching topologies, but even so, when considering the demand of high voltage in mobile electrified systems, heat generation is still a primary limiting factor in widespread adoption. Accordingly, the increased power density results in much higher temperatures at the device and package level, which in turn reduces the reliability of such systems, in terms of thermal breakdown or thermomechanical strains within the packages. As a result, the design of cooling systems for these electronics has emerged as a key component to successful implementation, and effective thermal management schemes must be closely integrated with the electronic packaging for maximum benefit. This review looks at various thermal management approaches that have been demonstrated in electronic systems, with a specific emphasis on the challenges and needs for next-generation high-voltage power electronics.

43 citations

01 Oct 1998

42 citations

Journal ArticleDOI
TL;DR: In this paper, the authors look at the entire cooling approach from the chip level all the way to the plenum level, and propose a solution with dimensions of $150~{rm mm} \times 300~{\rm mm] \times 38$ mm ( $H \times L \times W$ ).
Abstract: As the demand grows for electronics to become faster and more compact, the expectation for tomorrow’s data center is no different. Like many of the current high performance data center installations, design considerations on all scales must be taken into account. The proposed solution does just this by looking at the entire cooling approach from the chip level all the way to the plenum level. The solution’s enclosure, where all the heated elements are immersed in either FC-72 or Novec 649, has dimensions of $150~{\rm mm} \times 300~{\rm mm} \times 38$ mm ( $H \times L \times W$ ). The design is versatile allowing for either flow or pool boiling heat transfer. Under pool boiling conditions, heat transfer coefficients as high as 11.5 kW/ $\text{m}^{2}\,\cdot \,\text{K}$ were achieved with surface enhancements and maximum power dissipations as high as 320 W were yielded as chip temperatures were roughly 58 °C, well below typical operating conditions. With the introduction of dielectric fluid flow within the enclosure, maximum power dissipations achieved increased substantially, reaching 605 W, which corresponds to a volumetric power dissipation of 0.354 W/cm3.

24 citations