Juan Pablo Duarte

Bio: Juan Pablo Duarte is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: BSIM & MOSFET. The author has an hindex of 23, co-authored 55 publications receiving 1965 citations. Previous affiliations of Juan Pablo Duarte include KAIST.

Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

Abstract: We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Abstract: We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length $L_{g}=100$ nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau–Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective $S$ -shaped ferroelectric charge–voltage characteristics that provides important insights into the device operation.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

Abstract: A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

A Full-Range Drain Current Model for Double-Gate Junctionless Transistors

Abstract: A drain current model available for full-range operation is derived for long-channel double-gate junctionless transistors. Including dopant and mobile carrier charges, a continuous 1-D charge model is derived by extending the concept of parabolic potential approximation for the subthreshold and the linear regions. Based on the continuous charge model, the Pao-Sah integral is analytically carried out to obtain a continuous drain current model. The proposed model is appropriate for compact modeling, because it continuously captures the phenomenon of the bulk conduction mechanism in all regions of device operation, including the subthreshold, linear, and saturation regions. It is shown that the model is in complete agreement with the numerical simulations for crucial device parameters and all operational voltage ranges.

Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

Abstract: A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.

Technical manual : 日本語版

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Sustained Sub-60 mV/decade switching via the negative capacitance effect in MoS2 transistors

Abstract: It has been shown that a ferroelectric material integrated into the gate stack of a transistor can create an effective negative capacitance (NC) that allows the device to overcome “Boltzmann tyranny”. While this switching below the thermal limit has been observed with Si-based NC field-effect transistors (NC-FETs), the adaptation to 2D materials would enable a device that is scalable in operating voltage as well as size. In this work, we demonstrate sustained sub-60 mV/dec switching, with a minimum subthreshold swing (SS) of 6.07 mV/dec (average of 8.03 mV/dec over 4 orders of magnitude in drain current), by incorporating hafnium zirconium oxide (HfZrO2 or HZO) ferroelectric into the gate stack of a MoS2 2D-FET. By first fabricating and characterizing metal–ferroelectric–metal capacitors, the MoS2 is able to be transferred directly on top and characterized with both a standard and a negative capacitance gate stack. The 2D NC-FET exhibited marked enhancement in low-voltage switching behavior compared to th...

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

Abstract: An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Abstract: In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness of 9 nm and sub-15-nm gate length and NW width. Near-ideal subthreshold slope (SS) and extremely low leakage currents are demonstrated for ultrascaled gate lengths with a high on-off ratio (Ion/Ioff) >; 106. For the first time, an SS lower than 70 mV/dec is achieved at LG = 13 nm for n-type and p-type transistors, highlighting excellent electrostatic integrity of trigate junctionless NW MOSFETs.