Julie Widiez

Bio: Julie Widiez is an academic researcher from University of Grenoble. The author has contributed to research in topics: Germanium & Wafer. The author has an hindex of 22, co-authored 92 publications receiving 1403 citations. Previous affiliations of Julie Widiez include STMicroelectronics & University of Tokyo.

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Abstract: Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

3DVLSI with CoolCube process: An alternative path to scaling

Abstract: 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm2. This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Lasing in strained germanium microbridges.

Abstract: Germanium has long been regarded as a promising laser material for silicon based opto-electronics. It is CMOS-compatible and has a favourable band structure, which can be tuned by strain or alloying with Sn to become direct, as it was found to be required for interband semiconductor lasers. Here, we report lasing in the mid-infrared region (from λ = 3.20 μm up to λ = 3.66 μm) in tensile strained Ge microbridges uniaxially loaded above 5.4% up to 5.9% upon optical pumping, with a differential quantum efficiency close to 100% with a lower bound of 50% and a maximal operating temperature of 100 K. We also demonstrate the effect of a non-equilibrium electron distribution in k-space which reveals the importance of directness for lasing. With these achievements the strained Ge approach is shown to compare well to GeSn, in particular in terms of efficiency. Germanium (based) lasers are a promising route towards a fully CMOS-compatible light source, key to the further development of silicon photonics. Here, the authors realize lasing from strained germanium microbridges up to 100 K, finding a quantum efficiency close to 100%.

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

Abstract: Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated.

FinFETs and Other Multi-Gate Transistors

Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

The End of Moore's Law: A New Beginning for Information Technology

Abstract: The insights contained in Gordon Moore's now famous 1965 and 1975 papers have broadly guided the development of semiconductor electronics for over 50 years. However, the field-effect transistor is approaching some physical limits to further miniaturization, and the associated rising costs and reduced return on investment appear to be slowing the pace of development. Far from signaling an end to progress, this gradual "end of Moore's law" will open a new era in information technology as the focus of research and development shifts from miniaturization of long-established technologies to the coordinated introduction of new devices, new integration technologies, and new architectures for computing.

System comprising a semiconductor device and structure

Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Semiconductor device and structure

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Method for fabrication of a semiconductor device and structure

Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.