Julio C. Tinoco

Bio: Julio C. Tinoco is an academic researcher from Universidad Veracruzana. The author has contributed to research in topics: MOSFET & Transistor. The author has an hindex of 11, co-authored 52 publications receiving 384 citations. Previous affiliations of Julio C. Tinoco include Yahoo! & CINVESTAV.

Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Abstract: Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology Roadmap of Semiconductors projection, it is mandatory to find layout or technological solutions to reduce the total parasitic gate capacitance. In this context, it is necessary to develop a model that describes the parasitic capacitance in terms of the FinFET geometry. In this paper, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3-D numerical simulations, is presented. The model takes into account the external (five components) and internal (two components) fringing capacitances from the gate to the source/drain electrodes as well as the overlap capacitances. Comparisons with experimental results are presented to validate the developed model. Finally, based on the developed model, the evolution of the total parasitic gate capacitance as the channel length is reduced toward the 12-nm technology node is analyzed.

Impact of Extrinsic Capacitances on FinFET RF Performance

Abstract: Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of CMOS technology, because of their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations, we analyze the impact of the extrinsic gate capacitances on the RF behavior of FinFETs. It is shown that the reduction of the fin spacing, the modification of the fin geometrical aspect ratio (height/width) as well as the optimization of the fin spacing-fin Source/Drain extension ratio can significantly improve the FinFET RF performance.

High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors

Abstract: This work presents the high-temperature DC and RFbehaviorsofpartially-depletedSOI MOSFETs. DC and RF figures of merit are deeply investigated, both analytically and experimentally, to provide a complete study ofhigh-temperature performance and a comparison between floating-body and body-tied transistors. A highly stable RF performance is noticed especially for cutoff frequency and intrinsic elements for temperature as high as 250° C.

A comprehensive review on microwave FinFET modeling for progressing beyond the state of art

Abstract: FinFET is a multiple-gate silicon transistor structure that nowadays is attracting an extensive attention to progress further into the nanometer era by going beyond the downscaling limit of the conventional planar CMOS technology. Although the interest for this architecture has been mainly devoted to digital applications, the analysis at high frequency is crucial for targeting a successful mixed integration of analog and digital circuits. In view of that, the purpose of this review paper is to provide a clear and exhaustive understanding of the state of art, challenges, and future trends of the FinFET technology from a microwave modeling perspective. Inspired by the traditional modeling techniques for conventional MOSFETs, different strategies have been proposed over the last years to model the FinFET behavior at high frequencies. With the aim to support the development of this technology, a comparative study of the achieved results is carried out to gain both a useful feedback to investigate the microwave FinFET performance as well as a valuable modeling know-how. To accomplish a comprehensive review, all aspects of microwave modeling going from linear (also noise) to non-linear high-frequency models are addressed.

An investigation of annealing on the dielectric performance of TiO2 thin films

Abstract: The impact of annealing on the dielectric performance of TiO2 thin films synthesized by PECVD was investigated. Films annealed between 500 and 700 °C have an anatase crystal structure, while 800 °C annealed films display the rutile phase. The optimal annealing temperature was 600 °C, which both maximized the dielectric constant and minimized the leakage current density. The intrinsic dielectric constant of TiO2 improved from 82 ± 10 in as-deposited films to 168 ± 30 after annealing. The leakage current of optimized films was superior to the SiO2 control samples over a range of equivalent oxide thickness. Fowler–Nordheim tunnelling and Frenkel–Poole conduction were observed in the optimized films, while Schottky emission dominated leakage current at other conditions.

The structural and electrical properties of thermally grown TiO2 thin films

Abstract: We studied the structural and electrical properties of TiO2 thin films grown by thermal oxidation of e-beam evaporated Ti layers on Si substrates. Time of flight secondary ion mass spectroscopy (TOF-SIMS) was used to analyse the interfacial and chemical composition of the TiO2 thin films. Metal oxide semiconductor (MOS) capacitors with Pt or Al as the top electrode were fabricated to analyse electrical properties of the TiO2 thin films. We show that the reactivity of the Al top contact affects electrical properties of the oxide layers. The current transport mechanism in the TiO2 thin films is shown to be Poole–Frenkel (P–F) emission at room temperature. At 84 K, Fowler– Nordheim (F–N) tunnelling and trap-assisted tunnelling are observed. By comparing the electrical characteristics of thermally grown TiO2 thin films with the properties of those grown by other techniques reported in the literature, we suggest that, irrespective of the depositio nt echnique, annealing of as-deposited TiO2 in O2 is a similar process to thermal oxidation of Ti thin films.

Temperature Influence on GaN HEMT Equivalent Circuit

Abstract: The purpose of this letter is to present an experimental analysis of the temperature effects on the small-signal equivalent circuit of a GaN HEMT. With the aim of contributing to the exploration and advancement of this technology for high-power and high-temperature applications, the major intrinsic RF figures of merit together with the positive derivative of the real parts of the impedance parameters versus frequency are deeply investigated versus ambient temperature.