Showing papers by "Jun Fan published in 2002"

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Abstract: Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bits noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.

Enhancing signal path characteristics in a circuit board

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to. In another arrangement, clearances around vias at different power reference plane layers are selected to have different sizes to enhance the ability of one of the power reference plane layers (the one with a smaller clearance size) to carry a higher current level.

Reducing noise effects in circuit boards

Abstract: A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.

Characterizing multi-port cascaded networks

Abstract: A test mechanism includes test equipment to measure frequency-domain data, such as scattering or S parameters. The S parameters are transformed to a different type of network parameters, such as transmission or T parameters. Contributions of test fixtures can be easily removed for the overall T-parameter matrix of a device under test connected in cascade with the test fixture. The test mechanism provides accurate measurement of a device under test represented by a multi-port (greater than two ports) network that is cascaded with another multi-port network representing the test fixture.

Transmission line modeling of vias in differential signals

Abstract: Signal layer transitions in differential lines are modeled using both FDTD and equivalent circuit methods. The equivalent circuit is developed based on transmission-line reasoning regarding via behavior. Parameters of each transmission-line segment are obtained based on its corresponding physical geometry. The mixed-mode S-parameters from the equivalent circuit and the FDTD modeling are compared. Good agreement is demonstrated in the frequency range from 1 GHz to 20 GHz. The results indicate that vias in differential lines can be modeled as a transmission line for a quick and easy engineering estimation of the differential signal behavior in an environment of signal layer transitions.

Modeling noise coupling from non-parallel PCB trace routing

Abstract: Coupling between PCB signal traces in proximity is of concern to PCB designers and EMC engineers. The behavior of noise coupling between nonparallel microstrip lines is studied in this paper by a full-wave numerical modeling method CEMPIE, designating a circuit extraction approach based on a mixed-potential integral equation formulation. Good agreement between the numerical results and measurements was obtained.

Tailoring via impedance on a circuit board

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.

Extracting CAD models for quantifying noise coupling between vias in PCB layouts

Abstract: A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.

The effects of signal layer positions in multi-layer PCB designs

Abstract: In a high-speed multi-layer PCB (printed circuit board) design with multiple power layers, signal trace placement can be an important issue. Studies on a multi-layer test board are reported in this work. Single-ended high-speed signals that use the power layers as reference (return) may suffer extra loss in some frequency ranges due to the displacement current path from the power layer to ground. "Reference" capacitors are recommended as a solution to mitigate this effect. Differential traces do not suffer this extra loss. However, transmission loss and mode conversion of a differential trace may be affected by its layer position. The traces immediately adjacent to the ground layer showed the best performance in this particular test board.

Providing shields for systems

Abstract: A supplemental shield is used to cover a radiation leakage path through a chassis of the system. The supplemental shield is attached to at least one surface in the system to cover the radiation leakage path. In one arrangement, the supplemental shield has an adhesive portion to attach the supplemental shield to the at least one surface.