Showing papers by "Jun Fan published in 2004"

Effects of open stubs associated with plated through-hole vias in backpanel designs

Abstract: Plated through-hole (PTH) vias are commonly used in printed circuit boards. They usually leave open stubs if the signal(s) does not transition the entire depth of the board. These open stubs can have a negative impact on signal transmission. This summary reports the investigation of the impact of the open via stubs in a typical backpanel design.

A circuit approach to model narrow slot structures in a power bus

Abstract: A coupled transmission line model for narrow slot structures in DC power planes is proposed. This approach, combined with SPICE-based cavity models and a segmentation method, provides an easy and fast way to model relatively complex structures of power planes with narrow slots often used for isolation purposes. This approach is used to achieve isolation using gapping. The cavity model formulations for rectangular and isosceles right triangular segments are reviewed. The rationale of modeling the narrow slot as a three-conductor transmission line is described. The modeling results are shown and compared with the output of a full wave simulation tool, HFSS, and with experimental measurements.

Validation of equivalent circuits extracted from S-parameter data for eye-pattern evaluation

Abstract: S-parameter circuit model extraction is usually characterized by a trade off between accuracy and complexity. Trading one feature for another may or may not affect the goodness of the reconstructed S-parameter data, which are obtained from frequency domain simulations of the models extracted. However, the ultimate test for the validity of these equivalent circuit representations should be left to eye-diagram simulations, which provide useful insights, from an SI point of view, about the degradation of the signal, as it travels through the system. Physics based simplification procedures can be used to tune the models and achieve less complexity, whereas the comparisons of the eye-diagrams may help to quantify the goodness of all these circuits extracted. In fact, the most accurate model is not necessary the best to be used.

3D Modeling and Circuit Model Extraction of Vias in Multilayer Printed Circuit Boards

Abstract: The analysis of vias in multilayered geometries helps to improve the modeling of PCB’s and engineer a good solution from a signal integrity point of view [1-5]. The modeling of such elements is usually performed with full wave simulation tools. Although this is not an optimum approach for circuit analysis, it provides the insight needed for PCB layout. The extraction of circuit models to use in a SPICE tool avoids time consuming 3D simulations and simplifies the board design. Several methods can be employed to extract equivalent circuits from S-parameters, each of which is characterized by a trade-off between accuracy and complexity. Moreover, the need of an accurate model mainly depends upon the frequency range of interest, in fact, the wider the range is, the more complexity is needed in the equivalent circuit in order to reproduce the initial S-parameter data, which can be considered as the reference to estimate the accuracy of the model itself.

A time domain approach to estimate current draw from SMT decoupling capacitors

Abstract: A time domain approach to investigate and predict impedances and scattering parameters of a DC power bus is proposed. This approach is based on a cavity model and is achieved using a circuit simulation tool - SPICE. A SPICE-based circuit model for triangular power plane segments is described, verified and applied to simulate both the frequency and time domain characteristics of an irregularly shaped two-layer PCB board. Furthermore, the current draw from a surface mount technology (SMT) decoupling capacitor is simulated and estimated using this approach. Near-field electromagnetic loop probes are used to validate the current estimation qualitatively. Additionally, the frequency bandwidth of this SPICE model is investigated using a network analyzer and time domain reflectometry.

Method of forming a capacitor assembly in a circuit board

Abstract: A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.

Effects on crosstalk from a single-ended trace by referencing a non-ground reference plane

Abstract: The work studies the crosstalk issues between two single-ended traces when they reference a non-ground plane, such as a power plane Both near-end and far-end crosstalk may be enhanced at the distributed resonant frequencies associated with the printed circuit board Methods to decrease the crosstalk voltages are also investigated

Cabinet shielding inherent in standard equipment racks not designed to provide high-performance shielding

Abstract: Information technology equipment is often housed in racks enclosed as cabinets that are either poorly designed as electromagnetic shields or have not been specifically designed to provide high-performance shielding. This study examines the shielding characteristics of a class of computer systems each housed in similar cabinet racks that were not designed to provide significant levels of shielding. At frequencies above a few hundred MHz, these cabinet racks can provide shielding sufficient to be important in compliance with regulatory EMC requirements on radiated emissions. At frequencies lower than a few hundred MHz, these cabinet racks do not reliably provide significant shielding. These conclusions are based on radiated emissions testing of equipment racks with and without doors and side panels.

The design of a lumped element impedance-matching network with reduced parasitic effects obtained from numerical modeling

Abstract: This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the board-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated.