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Author

Jun Fan

Bio: Jun Fan is an academic researcher from Missouri University of Science and Technology. The author has contributed to research in topics: Equivalent circuit & Printed circuit board. The author has an hindex of 36, co-authored 482 publications receiving 5641 citations. Previous affiliations of Jun Fan include Ulsan National Institute of Science and Technology & University of Missouri.


Papers
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Proceedings ArticleDOI
20 Jun 2017
TL;DR: In this article, a method to predict the modulated noise coupling to an antenna is proposed and experimentally validated using a practical mobile phone, where the baseband noise of a liquid crystal display (LCD) is modulated with the Tx carrier signal of cellular communication, resulting in a radio frequency desensitization problem.
Abstract: A method to predict the modulated noise coupling to an antenna is proposed and experimentally validated using a practical mobile phone. The baseband noise of a liquid crystal display (LCD) is modulated with the Tx carrier signal of cellular communication, resulting in a radio frequency desensitization problem. The modulation mechanism is understood and its circuit representation is proposed to estimate the modulated noise coupling to an antenna. The modulation coefficient, which represents a relationship between the coupled voltage and modulated current, is experimentally extracted from a stand-alone LCD panel. The proposed modulation model is successfully validated through comparison with measurements using a practical mobile phone.

6 citations

Proceedings ArticleDOI
07 Nov 2002
TL;DR: The behavior of noise coupling between nonparallel microstrip lines is studied by a full-wave numerical modeling method CEMPIE, designating a circuit extraction approach based on a mixed-potential integral equation formulation.
Abstract: Coupling between PCB signal traces in proximity is of concern to PCB designers and EMC engineers. The behavior of noise coupling between nonparallel microstrip lines is studied in this paper by a full-wave numerical modeling method CEMPIE, designating a circuit extraction approach based on a mixed-potential integral equation formulation. Good agreement between the numerical results and measurements was obtained.

6 citations

Patent
14 May 2002
TL;DR: In this article, a circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, where power reference planes are provided, to connect signal lines at different signal layers.
Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.

6 citations

Journal ArticleDOI
TL;DR: In this paper, a partial-element equivalent circuit (PEEC) based circuit model was proposed to analyze the local region close to the slot, and it can be connected to the plane model and the transmission line model later.
Abstract: In this study, the structure that a stripline crosses with a narrow slot on the adjacent ground plane was rigorously studied in both a signal integrity and an electromagnetic interference point of view. A partial-element equivalent-circuit (PEEC) based circuit model was proposed to analyze the local region close to the slot, and it can be connected to the plane model and the transmission line model later. Based on an equivalent principal, the problem under a study can be converted to a mixed coupling problem between electrical surface current at the stripline and magnetic surface current on the slot. Therefore, the structure under the study can be treated as a complete cavity surrounded by the perfect electrical conductor at the top and bottom surfaces and a perfect magnetic conductor at four sides, so that the cavity Green's functions can be used in the PEEC formulation. The results obtained by the proposed method matched well with those obtained by a finite-element-based commercial tool.

6 citations

Journal ArticleDOI
TL;DR: Analysis results based on the proposed analytical model provide an in-depth understanding of and useful design guidance for on- chip power noise induced by the on-chip linear VRM with a high-speed output buffer.
Abstract: In this paper, analytical models of on-chip power noise induced by an on-chip linear voltage regulator module (VRM) circuit with a high-speed output buffer are proposed. Based on the piecewise linear approximated mosfet I – V curve model, closed-form equations for the on-chip power noise induced by an on-chip low-dropout regulator are derived. The accuracy of the proposed analytical model is validated by SPICE simulation with a 110-nm CMOS technology library. Based on the proposed analytical models, the impacts of VRM design parameters on VRM output noise induced by load current and external noises are analyzed. Because self-impedance at the VRM output and external noise transfer functions share a common resonant frequency, the on-chip power noise is minimized by avoiding the resonant frequency from peak frequencies of noise source spectrums. The larger on-chip decoupling capacitance at load reduces, the overall on-chip VRM output noise. While the larger pass transistor size reduces the on-chip VRM output noise induced by the reference voltage fluctuation, it increases the noise generated by off-chip power fluctuation. The reference voltage node needs to be carefully designed, as opposed to an off-chip power distribution network, due to its dominant impact on the on-chip VRM output noise. The analysis results based on the proposed model provide an in-depth understanding of and useful design guidance for on-chip power noise induced by the on-chip linear VRM with a high-speed output buffer.

5 citations


Cited by
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Journal ArticleDOI

[...]

08 Dec 2001-BMJ
TL;DR: There is, I think, something ethereal about i —the square root of minus one, which seems an odd beast at that time—an intruder hovering on the edge of reality.
Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

33,785 citations

01 Jan 2016

733 citations

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a wideband ultra wideband (UWB) communication protocol with a low EIRP level (−41.3dBm/MHz) for unlicensed operation between 3.1 and 10.6 GHz.
Abstract: Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

452 citations