J
Jun Fan
Researcher at Missouri University of Science and Technology
Publications - 505
Citations - 7033
Jun Fan is an academic researcher from Missouri University of Science and Technology. The author has contributed to research in topics: Printed circuit board & Equivalent circuit. The author has an hindex of 36, co-authored 482 publications receiving 5641 citations. Previous affiliations of Jun Fan include Ulsan National Institute of Science and Technology & University of Missouri.
Papers
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Proceedings ArticleDOI
The effects of signal layer positions in multi-layer PCB designs
TL;DR: In this article, reference capacitors are recommended as a solution to mitigate the effect of the displacement current path from the power layer to ground in a multi-layer printed circuit board.
Journal ArticleDOI
Objective MIMO Measurement
TL;DR: In this article, the authors proposed a new measurement method based on radiated two-stage approach for LTE systems to illustrate the relationship between the transmit power and the measured MIMO throughput.
Proceedings ArticleDOI
DC power bus modeling in high-speed digital designs including conductor and dielectric losses
TL;DR: In this paper, a circuit extraction approach based on a mixedpotential integral equation formulation is presented to model arbitrary multilayer power bus structures including vertical discontinuities associated with surface mount (SMT) decoupling capacitor interconnects.
Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk
Siqi Bai,Yuan-hai Liu,JongJoo Lee,Bichen Chen,Srinivasan Venkataraman,Xu Wang,Bo Pu,Jun Fan,DongHyun Kim +8 more
TL;DR: In this paper , a physical explanation for the power-via-induced quasi-quarter-wavelength resonance in differential signal pairs is proposed, and several PCB layouts are proposed to eliminate the power via-frequency resonance without the need to change the package pin map.
Proceedings ArticleDOI
Sensitivity Analysis of Local Soldermask and Coverlay in High Speed Transimission Lines for DDR5 Applications to Reduce FEXT
TL;DR: The effects of local solder-mask and overlay structure changes on crosstalk changes on a four-layer high-speed PCB on a computer DDR5 board are investigated to locate the optimal response that not only meets the performance requirements but is also robust to geometric changes caused by manufacturing tolerances.