Jun-Jie Wang

Bio: Jun-Jie Wang is an academic researcher from National Taiwan University. The author has contributed to research in topics: Routing (electronic design automation) & Rectilinear Steiner tree. The author has an hindex of 1, co-authored 2 publications receiving 7 citations.

Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction

Abstract: As Engineering Change Order (ECO) has attracted substantial attention in modern VLSI design, the open net problem, which aims at constructing a shortest obstacle-avoiding path to reconnect the net shapes in an open net, becomes more critical in the ECO stage. This paper addresses a multi-layer obstacle-avoiding region-to-region Steiner minimal tree (SMT) construction problem that connects all net shapes by edges on a layer or vias between layers, and avoids running through any obstacle with a minimal total cost. Existing multi-layer obstacle-avoiding SMT algorithms consider pin-to-pin connections instead of region-to-region ones, which would limit the solution quality due to its lacking region information. In this paper, we present an efficient algorithm based on our new multi-layer obstacle-avoiding region-to-region spanning graph to solve the addressed problem, which guarantees to find an optimal solution for a net connecting two regions on a single layer. Experimental results show that our algorithm outperforms all the participating routers of the 2017 CAD Contest at ICCAD in both solution quality and runtime.

Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems

Abstract: A multi-FPGA system consists of multiple FPGAs connected by physical wires, and a circuit is partitioned to fit each FPGA and routed on the system by such physical wires. Due to the limited numbers of input/output (I/O) pins in an FPGA, however, not all signals can be transmitted between FPGAs directly. Moreover, the routing resource may not be sufficient to accommodate many cross-FPGA signals from circuit partitioning. As a result, input/output time-division multiplexing (TDM) is introduced to send a group of cross-FPGA signals in a routing channel with a timing penalty. To optimize the performance of such a system, we shall develop a simultaneous partitioning and routing algorithm considering the timing penalty caused by I/O TDM. Considering the TDM delay penalty, we propose a simultaneous partitioning and routing algorithm to remedy the insufficiency of the two-stage flow of partitioning followed by routing. Our algorithm consists of two major steps: (1) a novel routing-aware partitioning framework to obtain an initial solution considering irregular, asymmetric connections, and (2) a partition-aware routing scheme to optimize routing in each partitioning pass. Experimental results show that our proposed algorithm can achieve better timing than the classical flow.

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

Abstract: Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

Abstract: The rectilinear/octilinear Steiner problem is the problem of connecting a set of terminals $Z$ using orthogonal and diagonal edges with minimum length. This problem has many applications, such as the EDA, VLSI circuit design, fault-tolerant routing in mesh-based broadcast, and Printed Circuit Board (PCB). This paper proposes an obstacle-avoiding 4/8/10/26-directional heuristic algorithm for this problem based on the Areibi’s concept, Higher Geometry Maze Routing, and Sollin’s minimal spanning tree algorithm. The major contributions of this paper are (1) our work is the first report for the octilinear SMTs in the multidimensional environments, (2) we provide an optimal point-to-point routing without any refinement, and (3) the proposed algorithm has higher adaptability to deal with any irregular environment, and can be extended to the $\lambda $ -geometry without any extra work, where $\lambda =2$ , 4, 8 and $\infty $ corresponding to rectilinear, 45°, 22.5° and Euclidean geometries respectively.

An Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Method Using PB-SAT

Abstract: Rectilinear Steiner tree (RST) construction is an important part of recent VLSI physical design. This article presents an efficient satisfiability (SAT) based approach to construct an obstacle-avoi...

Performance-Driven X-Architecture Routing Algorithm for Artificial Intelligence Chip Design in Smart Manufacturing

Abstract: The new 7-nm Artificial Intelligence (AI) chip is an important milestone recently announced by the IBM research team, with a very important optimization goal of performance. This chip technology can be extended to various business scenarios in the Internet of Things. As the basic model for very large scale integration routing, the Steiner minimal tree can be used in various practical problems, such as wirelength optimization and timing closure. Further considering the X-architecture and the routing resources within obstacles, an effective performance-driven X-architecture routing algorithm for AI chip design in smart manufacturing is proposed to improve the delay performance of the chip. First, a special particle swarm optimization algorithm is presented to solve the discrete length-restricted X-architecture Steiner minimum tree problem in combination with genetic operations, and a particle encoding scheme is presented to encode each particle into an initial routing tree. Second, two lookup tables based on pins and obstacles are established to provide a fast information query for the whole algorithm flow. Third, a strategy of candidate point selection is designed to make the particles satisfy the constraints. Finally, a refinement strategy is implemented to further improve the quality of the final routing tree. Compared with other state-of-the-art algorithms, the proposed algorithm achieves a better total wirelength, which is an important index of performance, thus better satisfying the demand for delay performance of AI chip design in smart manufacturing.

Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction

Abstract: Engineering change orders (ECOs) are pervasively applied to modern physical design of nanometer integrated circuits for cost-effective design changes. After applying ECO, a net may become open, which results in a large number of disconnected net components. Each net component further consists of a set of connected net shapes and vias on different layers. It is very challenging to efficiently and effectively identify all disconnected net components and find an obstacle-avoiding minimal-cost routing path among those net components. This paper introduces an open-net finder and an open-net connector based on the corner-stitching data structure for open-net routing, and proposes a new method of constructing a multilayer obstacle-avoiding component-to-component rectilinear minimum spanning tree. The preliminary idea and implementation of the proposed method had received the first place award in ICCAD-2017 CAD contest. This paper further details the complete idea of the proposed method. Experimental results show that the proposed open-net finder and connector outperform the top three open-net routers in the ICCAD-2017 CAD contest and two latest published works, with better routing costs and much shorter runtime.