J
Jun Sawada
Researcher at IBM
Publications - 56
Citations - 5615
Jun Sawada is an academic researcher from IBM. The author has contributed to research in topics: TrueNorth & Electronic circuit. The author has an hindex of 17, co-authored 56 publications receiving 4315 citations.
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Journal ArticleDOI
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla,John V. Arthur,Rodrigo Alvarez-Icaza,Andrew S. Cassidy,Jun Sawada,Filipp Akopyan,Bryan L. Jackson,Nabil Imam,Chen Guo,Yutaka Nakamura,Bernard Brezzo,Ivan Vo,Steven K. Esser,Rathinakumar Appuswamy,Brian Taba,Arnon Amir,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +19 more
TL;DR: Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.
Journal ArticleDOI
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Filipp Akopyan,Jun Sawada,Andrew S. Cassidy,Rodrigo Alvarez-Icaza,John V. Arthur,Paul A. Merolla,Nabil Imam,Yutaka Nakamura,Pallab Datta,Gi-Joon Nam,Brian Taba,Michael P. Beakes,Bernard Brezzo,Jente B. Kuang,Rajit Manohar,William P. Risk,Bryan L. Jackson,Dharmendra S. Modha +17 more
TL;DR: This work developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture, and successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition.
Proceedings ArticleDOI
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores
Andrew S. Cassidy,Paul A. Merolla,John V. Arthur,Steve K. Esser,Bryan L. Jackson,Rodrigo Alvarez-Icaza,Pallab Datta,Jun Sawada,Theodore M. Wong,Vitaly Feldman,Arnon Amir,Daniel D Ben Dayan Rubin,Filipp Akopyan,Emmett McQuinn,William P. Risk,Dharmendra S. Modha +15 more
TL;DR: A simple, digital, reconfigurable, versatile spiking neuron model that supports one-to-one equivalence between hardware and simulation and is implementable using only 1272 ASIC gates is developed.
Journal ArticleDOI
TrueNorth: Accelerating From Zero to 64 Million Neurons in 10 Years
Michael DeBole,Brian Taba,Arnon Amir,Filipp Akopyan,Alexander Andreopoulos,William P. Risk,Jeff Kusnitz,Carlos Tadeo Ortega Otero,Tapan K. Nayak,Rathinakumar Appuswamy,Peter J. Carlson,Andrew S. Cassidy,Pallab Datta,Steven K. Esser,Guillaume J. Garreau,Kevin L. Holland,Scott Lekuch,Michael Mastro,Jeffrey L. McKinstry,Carmelo di Nolfo,Brent Paulovicks,Jun Sawada,Kai Schleupen,Benjamin G. Shaw,Klamo Jennifer,Myron D. Flickner,John V. Arthur,Dharmendra S. Modha +27 more
TL;DR: IBM's brain-inspired processor is a massively parallel neural network inference engine containing 1 million spiking neurons and 256 million low-precision synapses, making it the largest neurosynaptic computer ever built.
Proceedings ArticleDOI
A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS
Leland Chang,Yutaka Nakamura,R. K. Montoye,Jun Sawada,Andrew K. Martin,K. Kinoshita,Fadi H. Gebara,Kanak B. Agarwal,Dhruva Acharyya,Wilfried Haensch,Kohji Hosokawa,Damir A. Jamsek +11 more
TL;DR: In this article, a 32-kb subarray is implemented with a 65 nm node 8T-SRAM cell for variability tolerance in high-speed caches, achieving 5.3 GHz operation at 1.2 V.