Planar circuits for microwaves and lightwaves

Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

Power distribution system design methodology and capacitor selection for modern CMOS technology

The theoretical and experimental evaluation of the cyclostationary random data transferring process corrupted by the individually and jointly cyclostationary crosstalk interference is presented. The interference and the message signals were measured by the real time digital oscilloscope. Autocorrelation functions were evaluated by synchronous cyclic averaging procedure. The analyzed periodic two-dimensional impulse response of the time-varying filter allows to obtain the output random process with the same cyclic frequency at the output of the filter by separation of orthogonal stationary waveforms constituting the input cyclostationary random process (CSRP). The filtering of the measured random process was implemented by the cyclic Wiener filter. The evaluation of the two-dimensional autocorrelation function and eye diagrams at the output of the cyclic Wiener filter showed significant reduction of the independent interference components in the estimated message signal.

Cyclostationary Crosstalk Cancelation in High-Speed Transmission Lines

With rapidly increasing switching speeds and surge current requirements, placement of local decoupling capacitors is becoming critically important in high-speed low-power designs. In this paper, utilizing the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits. In the proposed approach, instead of using the traditional trial-and-error method to identify an appropriate placement distance, the process is formulated in the form of a transcendental function. The resulting function is solved using Newton–Raphson (N-R) iterations to give a direct solution for the distance. Also, an analytical representation based on Hankel functions for the driving point impedance and its derivatives is developed to speed up the N-R iterations. The proposed method is validated by comparing the results with the full-wave electromagnetic simulations.

Efficient Decoupling Capacitor Placement Based on Driving Point Impedance

A semi-analytical method is proposed to evaluate the effectiveness of a decoupling capacitor on resonant power and ground planes. New expressions are developed relating the pin impedance to relative placement of a capacitor with associated angular and distance parameters. To speed up the solution of resulting transcendental equations, a 2-D iterative technique is proposed, which yields the effective distance as well as the angle between a decoupling capacitor and a power pin. The partial derivatives of the corresponding Jacobian matrix are analytically derived. Numerical examples are presented to demonstrate the validity of the proposed method, which also investigates the effect of plane edges on pin impedance.

Decoupling Capacitor Placement on Resonant Parallel-Plates Via Driving Point Impedance

Based on the resonant cavity model, this paper presents a modeling approach for power/ground planes with decoupling capacitors. A bare plane pair is first modeled by the resonant cavity model. Then, decoupling capacitors are divided into segments according to port coefficients, capacitance, the number of decoupling capacitors, and the frequency response of each mode of the resonant cavity model. To get the model of the plane pair with decoupling capacitors, divided segments are incorporated into the resonant cavity model. By this way, not only the influence of decoupling capacitors on each single mode, but also the frequency responses of capacitors in each mode can be reflected. By being incorporated with the segmentation method and the physics-based modeling method, this modeling method can be extended to handle the irregular-shaped and multilayered power/ground plane with capacitors, respectively. Based on the impedance distribution throughout the whole power/ground plane pair, the effective decoupling radius of a capacitor and its variation trends with frequency, capacitance, and parasitic parameters are extracted and analyzed.

Modeling and Simulation of Planes With Decoupling Capacitors

As the clock frequency of a chip increases, the on-chip decoupling capacitor must be placed closer to the load to be effective A method of efficiently defining the location of capacitor placement to meet specified noise limits is presented Based on a single RL line model for the power distribution system, charging radius of the decoupling capacitor is calculated under the constraint of the target noise but not the constraint of being fully charged Under the constraints of the length of the charging path and the target noise, discharging radius of the decoupling capacitor is figured out The conversion coefficient that converts the radii of a decoupling capacitor in a single RL line model into the equivalent one in a meshed model is presented based on the expression that can exactly compute the impedance between any two points on an infinite meshed network In this paper, it is shown that the conversion coefficient is a constant when the radius of the decoupling capacitor is taken as the per unit length of the meshed model

Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint

Target tracking in passive multi-static radar (PMSR) with bistatic range and Doppler frequency measurements from multiple transmit–receive pairs is gaining increasing interest. For the data association problem in this scenario, the parallel architecture of a multi-sensor joint probabilistic data association (P-MSJPDA) filter has been significantly investigated. As an alternative architecture, the sequential MSJPDA (S-MSJPDA) is rarely discussed in PMSR. In this paper, we evaluate the behaviors of S-MSJPDA in PMSR target tracking with bistatic range and Doppler frequency measurements. A comprehensive comparison between the S-MSJPDA and the P-MSJPDA in PMSR is provided. It can be found from the analysis that S-MSJPDA outperforms its parallel counterpart in terms of computational efficiency, given an acceptable degradation in position accuracy. The S-MSJPDA is further applied to an experimental passive multi-static radar for aircrafts tracking. The real data results obtained are rather close to the true trajectories of the targets. This demonstrates that the S-MSJPDA has great potentials in PMSR target tracking.

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Sequential Multi-Sensor JPDA for Target Tracking in Passive Multi-Static Radar With Range and Doppler Measurements

This paper proposes a decoupling capacitor placement optimization method based on the cavity model and Lagrange multiplier. The variable conditions associating with coordinates (x,y) of input impedance expression based on the cavity model are combined with the Lagrange multiplier method. The decoupling capacitor optimum placement within a defined area of the board can be found through the proposed analytical method. The example of finding an optimum location of the decoupling capacitor within a defined area of the power delivery network is exposed, the results are compared to the brute-force method to prove the effectiveness of the proposed method.

Decoupling Capacitor Placement Optimization With Lagrange Multiplier Method

For high-speed coding buses, it is a great challenge to evaluate the eye diagram accurately. Assuming that all data bits are independent and have uniform probabilities as previous estimation methods have done is not valid. In this paper, a new statistical method is proposed to estimate the worst-case eye diagrams and bit-error-rate (BER) eye diagrams for coding buses. The probability distribution of coded bus bit vectors is modeled based on the coding rule constraints. Then, actual worst pattern and eye diagram calculation is derived based on bus bit transition probabilities and double-edge responses. In order to validate the method, a parallel link with data bus inversion coding and 4b/6b coding is simulated, respectively. Worst case eye diagrams and BER eye diagrams are calculated and compared with that of no consideration of coding. Compared to the traditional statistical methods, this method eliminates the error due to the invalid assumption and provides more accurate results for designers.

Jun Wang

Papers

Modeling and Simulation of Planes With Decoupling Capacitors

Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint

Sequential Multi-Sensor JPDA for Target Tracking in Passive Multi-Static Radar With Range and Doppler Measurements

Decoupling Capacitor Placement Optimization With Lagrange Multiplier Method

Statistical Eye Diagram Analysis Based on Double-Edge Responses for Coding Buses