This paper presents the design and implementation of a 4 $\times$ 4 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) baseband receiver for indoor high-throughput wireless communication systems. The receiver uses bandwidths of 40, 80, and 160 MHz that correspond to three operation modes of 128, 256, and 512-point FFT, respectively. Four spatial streams are supported to offer the maximum uncoded data rate of 2.6 Gbps. Channel pre-processing based on sorted QR decomposition and the non-constant K-best soft-output MIMO detector are adopted to enhance the system performance. The addressing scheme for the QR phase memory is proposed to deal with the processing-time discrepancy between the write-in and read-out accesses. The high-throughput pipelined architecture for the non-constant K-best soft-output MIMO detector with selected discard-paths is analyzed to show a balance between performance and complexity. This receiver IC integrates 1.034 M logic gates as well as a total of 835 Kb SRAM in 90 nm CMOS technology and can generate hard output for 64-QAM constellation. The coded system performance is also provided with the soft-output MIMO detection. From the measurement results, the power consumption of the chip is 424 mW, 97 mW, and 26 mW at 1.16 V, 0.8 V and 0.66 V, respectively, for operations in 160 MHz, 80 MHz, and 40 MHz bandwidth modes. Compared to the prior works for 80 MHz channel bandwidth, this work supports wider channel bandwidth and achieves higher throughput.

A 4 $\times$ 4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications

Silicon implementation of iterative detection and decoding for multi-antenna receivers

Fixed-Complexity Sphere Decoder (FSD) is an quasi-optimal detector for Multiple-Input Multiple-Output (MIMO) system which is a hardware-friendly parallel tree-search customised to the modulation and antenna scheme employed. However, it is not able to adapt its behaviour for various modulation and antenna schemes, as demanded by modern wireless standard. This restricts its usage in modern adaptive MIMO systems. This paper proposes a solution to this problem. A configurable FSD structure in proposed where normalized higher order modulation schemes can accommodate lower ones. By exploiting clock-gating, FSD of all modulation schemes is equally trimmed to allow power savings of over 30% when implementing on Field Programmable Gate Array (FPGA). This architecture enables the facility to balance the power consumptions with compatible information rate in dynamic, adaptive MIMO communications environments.

Energy-Efficient Adaptive Modulated Fixed-Complexity Sphere Decoder

Soft-input soft-output (SISO) sphere decoding is applied to multiple-input multi-output (MIMO) systems to offer good bit error rate (BER) performance but at high complexity. To reduce this computational complexity, we propose a novel hybrid enumeration strategy for such decoding that dynamically determines the candidate list; moreover, this strategy uses a new node enumeration based on concentric circles. Specifically, points in an MQAM constellation diagram are divided into several subsets; and the visiting order among subsets is predefined by the concentric circle locations. Simulation results demonstrate that the proposed enumeration strategy outperform previous approach, while keeping a low complexity.

Efficient node enumeration for soft-input soft-output sphere decoding

By exchanging soft information between the detector and the channel decoder, an iterative receiver can significantly improve the performance compared to the non-iterative receiver. In this paper, a low complexity soft-input soft-output (SISO) fixed-complexity sphere decoding (FSD) algorithm is proposed for iterative MIMO receiver. The algorithm introduces a simplified parallel candidate adding (SPCA) scheme to provide more accurate soft information. Furthermore, by employing our proposed improved hybrid-enumeration method, the SISO-FSD can reduce the computational complexity substantially. Simulation results show that the algorithm can achieve a near Max-Log optimal maximum a posteriori (MAP) detection performance under flat fading Rayleigh channels. Compared to the SISO K-Best algorithm (K=50), the proposed algorithm saves about 60% computations and provides almost the same performance for detecting 4×4 64-QAM MIMO signal, making it a promising scheme for real-life hardware implementation.

A Low Complexity Soft-Input Soft-Output Fixed-Complexity Sphere Decoding Algorithm

Multiple-input multiple-output (MIMO) technique can significantly increase data throughput without sacrificing additional bandwidth. This paper proposes a soft-output K-Best detector for 4×4 64-QAM MIMO system to achieve Gbps throughput. The key contribution of this work is proposing the relaxed 2-parallelism sorting scheme which can produce two survivor paths simultaneously, thus significantly improve the throughput. Furthermore, utilization of upper levels' discarded paths (DPs) and direct zero forcing (ZF)-augmentation to survivor paths in last two stages are adopted to obtain good BER performance with low complexity. This proposed detector outperforms the conventional soft-output K-Best scheme by 3.5dB at BER=10-4 when using the minimum mean squared error-sorted QR decomposition (MMSE-SQRD) channel preprocessing. Fabricated in SMIC 0.13μm CMOS, the VLSI implementation achieves a peak throughput of 1.368 Gbps and consumes 84 cycles for latency.

Junfeng Wang

Papers

A Low Complexity Soft-Input Soft-Output Fixed-Complexity Sphere Decoding Algorithm

Gbps Soft-Output K-Best MIMO Detector Design with Relaxed Parallel Sorting