Junil Lee

Bio: Junil Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Transistor & Coercivity. The author has an hindex of 7, co-authored 38 publications receiving 178 citations. Previous affiliations of Junil Lee include Inha University.

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Abstract: In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.

Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs

Abstract: In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

Abstract: By using technology computer aided design (TCAD) simulation, the aim of this paper is to investigate the effect of Si parasitic channel, which is placed under stacked nanosheet channels, on electrical characteristic of stacked nanosheet GAA FETs. We have controlled the parasitic channel height, and evaluated the effect on electrical performance of the device. Trade-off in performance of the nanosheet FET is observed: the increase in parasitic channel height results in improvement in subthreshold swing and on/off ratio, while the increase in capacitance brings worse RC delay and active power. The parasitic channel height control in devices with ground plane doping is also investigated.

Effects of Localized Body Doping on Switching Characteristics of Tunnel FET Inverters With Vertical Structures

Abstract: In order to verify the effects of localized body doping (LBD) on alternating current switching performances of tunnel FETs (TFETs) with vertical structures, The TFET inverter composed of n-/p-type TFET with the localized p+/n+ body doping is simulated with the help of mixed-mode device and circuit simulations. As a result, falling/rising delay is significantly improved due to the locally high channel-to-drain side energy barrier induced by the LBD. Furthermore, LBD conditions, such as doping concentration, depth, and width, are optimized to maximize the improvement of falling/rising delay. Based on the optimization results, it is found that enough wide doping width and deep depth are inevitable to minimize the drain voltage ( ${V} _{D}$ )-induced lowering of the locally increased barrier and the increase of ambipolar current and too wide doping width cannot be applied due to the ON-current reduction caused by the degraded controllability of gate voltage on channel similarly to short channel effects. Moreover, the doping width and depth should be adjusted according to LBD concentration.

Assessment of dry etching damage in permalloy thin films

Abstract: Permalloy (Ni81Fe19) thin films are etched by ion beam etching (IBE) or reactive ion etching (RIE), and the variation of magnetic properties with etching time is investigated. Magnetic softness of permalloy thin films deteriorates as etching proceeds, i.e., film thickness decreases. Coercivity begins to increase steeply at a thickness of 0.4 μm and reaches 16 Oe for IBE and 8 Oe for RIE at 0.09 μm. Effective magnetization is increased by 0.2 kG with IBE but decreased by 0.7 kG with RIE. From an atomic force microscopy analysis and independent wet etching experiments, the increase of coercivity is proved to be attributed to the increase of surface roughness as a result of etching. Etching-induced defects are also responsible for the increase of coercivity, which is confirmed by a measurement of electrical resistivity and x-ray diffraction analysis. Ion beam etching process appears to affect magnetic properties to a greater extent than reactive ion etching process.

A comprehensive review on emerging artificial neuromorphic devices

Abstract: The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

Integrated inductive components and method of fabricating such components

Abstract: An inductive component includes a substrate (12) on the surface of which is a lower insulation layer (32) having a shallow concavity (34) or trench, a first plurality of conductive elements (16) formed in the trench, a magnetic core (14) formed over the first plurality of conductive elements, and a second plurality of conductive elements (18) formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers (28, 30) are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques. A first array of conductors (16) is patterned over the lower insulation layer (34), and a first core insulation layer (28) is applied over the first conductor array. A magnetic core (14) is formed on top of the first core insulation layer, and a second core insulation layer (30) is applied over the core. A second array of conductors (18) is patterned on top of the second core insulation layer so that the ends of the conductors in the first and second arrays contact each other to form an inductive coil around the core. The formation of either the first or second plurality of conductors may coincide with the formation of the metal conductor layer in the manufacture of a semiconductor integrated circuit, whereby the inductive component can be manufactured as part of the integrated circuit.

Method of fabricating a micro-technical structure, and micro-technical component

Abstract: The invention relates to a method for fabricating in particular a TMR element for use in a MRAM, wherein a mask is arranged on a substrate and structured in such a manner that it shadows but does not cover a surface region of the substrate, and wherein material of the structure which is to be fabricated is then deposited on the substrate in a directed deposition process. The invention also relates to a component with a micro-technical structure which has been fabricated in this manner.