Junlin Chen

Bio: Junlin Chen is an academic researcher from University of Connecticut. The author has contributed to research in topics: Energy (signal processing) & Efficient energy use. The author has an hindex of 6, co-authored 11 publications receiving 253 citations.

A Survey on Chip to System Reverse Engineering

Abstract: The reverse engineering (RE) of electronic chips and systems can be used with honest and dishonest intentions. To inhibit RE for those with dishonest intentions (e.g., piracy and counterfeiting), it is important that the community is aware of the state-of-the-art capabilities available to attackers today. In this article, we will be presenting a survey of RE and anti-RE techniques on the chip, board, and system levels. We also highlight the current challenges and limitations of anti-RE and the research needed to overcome them. This survey should be of interest to both governmental and industrial bodies whose critical systems and intellectual property (IP) require protection from foreign enemies and counterfeiters who possess advanced RE capabilities.

Chip-level anti-reverse engineering using transformable interconnects

Abstract: Cloning of integrated circuit (IC) chips have emerged as a significant threat to the semiconductor industry. Unauthorized extraction of design information from IC chips can be carried out in numerous ways. Invasive methods physically disassemble chip package and gain access to the different layers of a die through the low-cost delaying processing. This paper presents a new countermeasure exploiting transformable IC technologies. Transformable ICs are fabricated using materials that not only are electronically active but also change their electrical properties and physical compositions when experiencing invasive attacks. Simulation results demonstrate the proposed approach in improving the complexity of chip reverse engineering without introducing large performance overhead.

Energy-Adaptive Modulation for RF Power Management under Renewable Energy

Abstract: This paper presents a new power management technique for RF circuits powered by renewable energy sources. Different from conventional systems, the performance of self-powered RF circuits is largely constrained by two factors: time-varying fading channel conditions and non-deterministic renewable energy levels. The proposed technique dynamically adjusts the base band modulation scheme to deal with these two factors in a coherent manner in order to maximize the data rate of RF circuits. Some practical issues, such as battery aging, have been investigated. The proposed technique is shown to be robust and insensitive to these issues. Simulation results demonstrate that the proposed technique outperforms conventional approaches based on fixed modulation schemes under various conditions.

A Chip-Level Anti-Reverse Engineering Technique

Abstract: Protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. However, advanced reverse engineering techniques can physically disassemble the chip and derive the IPs at a much lower cost than the value of IP design that chips carry. This invasive hardware attack—obtaining information from IC chips—always violates the IP rights of vendors. The intent of this article is to present a chip-level reverse engineering resilient design technique. In the proposed technique, transformable interconnects enable an IC chip to maintain functioning in normal use and to transform its physical structure into another pattern when exposed to invasive attacks. The newly created pattern will significantly increase the difficulty of reverse engineering. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead.

Link and energy adaptive UWB-based embedded sensing with renewable energy

Abstract: A new link and energy adaptive UWB-based sensing system is proposed to maximize the detection time coverage of UWB-based pulse radar in embedded sensing applications powered by renewable energy. By jointly considering the link information between the transmitter and receiver of the UWB radar as well as the non-deterministic characteristics of the renewable energy, the proposed system dynamically adjusts the pulse repetition frequency of the UWB radar to enhance the energy efficiency. Simulation results demonstrate that the proposed system can significantly improve the average detection time coverage as compared with the conventional system. The proposed technique is also insensitive to battery issues such as limited battery capacity.

31p-S-4 Giant Magnetoresistance in Magnetic Manganese Oxide with Intrinsic Antiferromagnetic Spin Structure

Abstract: Giant and isotropic magnetoresistance as huge as −53% was observed in magnetic manganese oxide La0.72Ca0.25MnOz films with an intrinsic antiferromagnetic spin structure. We ascribe this magnetoresistance to spin‐dependent electron scattering due to spin canting of the manganese oxide.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits

Abstract: Logic locking and IC camouflaging are proactive circuit obfuscation methods that if proven secure can thwart hardware attacks such as reverse engineering and IP theft. However, the security of both these schemes is called into question by recent SAT based attacks. While a number of methods have been proposed in literature that exponentially increase the running time of such attacks, they are vulnerable to "findand-remove" attacks, and only slightly hide the circuit functionality. In this paper, we present a novel approach towards creating SAT attack resiliency based on creating densely cyclic obfuscated circuit topologies by adding dummy paths to the circuit. Our methodology is applicable to both IC camouflaging and logic locking. We demonstrate that cyclic logic locking creates SAT resilient circuits with 40% less area and 20% less delay compared to an insecure XOR/XNOR-obfuscation with the same key length. Furthermore, we show that cyclic IC camouflaging can be implemented at the layout level with no substrate area overhead and little delay and power overhead with respect to the original circuit.

Provably secure camouflaging strategy for IC protection

Abstract: The advancing of reverse engineering techniques has complicated the efforts in intellectual property protection. Proactive methods have been developed recently, among which layout-level IC camouflaging is the leading example. However, existing camouflaging methods are rarely supported by provably secure criteria, which further leads to over-estimation of the security level when countering the latest de-camouflaging attacks, e.g., the SAT-based attack. In this paper, a quantitative security criterion is proposed for de-camouflaging complexity measurements and formally analyzed through the demonstration of the equivalence between the existing de-camouflaging strategy and the active learning scheme. Supported by the new security criterion, two novel camouflaging techniques are proposed, the low-overhead camouflaging cell library and the AND-tree structure, to help achieve exponentially increasing security levels at the cost of linearly increasing performance overhead on the circuit under protection. A provably secure camouflaging framework is then developed by combining these two techniques. Experimental results using the security criterion show that the camouflaged circuits with the proposed framework are of high resilience against the SAT-based attack with negligible performance overhead.

CamoPerturb: secure IC camouflaging for minterm protection

Abstract: Integrated circuit (IC) camouflaging is a layout-level technique that thwarts reverse engineering attacks on ICs by introducing camouflaged cells that look alike, but can implement one of many possible Boolean functions. Existing camouflaging techniques have been broken by a recent decamouflaging attack, which uses Boolean satisfiability (SAT) techniques to compute specialized discriminating input patterns that prune the functionality search space quickly. This paper presents CamoPerturb, a countermeasure to thwart the decamouflaging attack by integrating logic perturbation with IC camouflaging. CamoPerturb, contrary to all the existing camouflaging schemes, perturbs the functionality of the given design minimally, i.e., adds/removes one minterm, rather than camouflaging the design. A separate camouflaged block CamoFix restores the perturbed minterm, recovering the functionality of the design. The perturbed minterm is the designer's secret and is incorporated into CamoFix using camouflaged cells. CamoPerturb renders the decamouflaging attack effort exponentially harder in the number of camouflaged gates while its overhead grows linearly. The paper presents formal proofs for the security of CamoPerturb along with experimental results.