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Jussi Jansson

Bio: Jussi Jansson is an academic researcher from University of Oulu. The author has contributed to research in topics: CMOS & Time-to-digital converter. The author has an hindex of 3, co-authored 4 publications receiving 295 citations.

Papers
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Journal ArticleDOI
TL;DR: A high-precision CMOS time-to-digital converter IC has been designed based on a counter and two-level interpolation realized with stabilized delay lines that reduces the number of delay elements and registers and lowers the power consumption.
Abstract: A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.

272 citations

Proceedings ArticleDOI
23 May 2005
TL;DR: An integrated digital CMOS time-to-digital converter which measures time periods with picosecond-level resolution is introduced, using a counter and a two-level nested DLL interpolation.
Abstract: This paper introduces an integrated digital CMOS time-to-digital converter which measures time periods with picosecond-level resolution. The circuit was fabricated in a 0.35 /spl mu/m standard digital CMOS process. 13 ps rms single-shot precision was achieved by using a counter and a two-level nested DLL interpolation. Interpolators, which divide the cycle time of the 145 MHz reference clock to 512 pieces, provided 13.5 ps LSB width. The temperature drift was below 0.05 ps//spl deg/C. The power consumption with a 3.3 V operating voltage was 55 mW.

28 citations

Proceedings ArticleDOI
07 May 2009
TL;DR: In this paper, a straight-forward leading edge type of receiver that detects the cross-over of the received pulse with respect to a set reference level was proposed to realize the timing detection of the laser pulses.
Abstract: Pulsed time-of-flight laser ranging is based on measuring the transit time of a short laser pulse to an optically visible target and back to the receiver. These techniques are gaining in popularity for industrial distance measurement applications. The laser pulse length typically used is in the range of 3 ns, which corresponds to about 1 m in air. This pulse length poses a challenge for detection of the echo from the target since the accuracy aimed at in a single shot is typically at the level of a few centimetres or even better with a dynamic range of more than 1:10 000. This paper studies the possibility of realizing the timing detection of the laser pulses with a straight-forward leading edge type of receiver that detects the cross-over of the received pulse with respect to a set reference level. Without any other measures the timing walk error that would be produced with this kind of receiver, would be at the level of nanoseconds. However, by measuring either the width or the slew rate of the rising edge of the received pulse, timing walk can be compensated for based on the measured dependence of the walk on the respective parameter. The advantage of these methods is that they are effective even when the optoelectronic receiver is saturated, thus enabling one to achieve wide dynamic operating range. Using these time-domain walk compensation methods we have constructed fully integrated CMOS and BiCMOS laser radar receivers that achieve timing walk error of less than +/-30ps in dynamic range of 1:10 000 -100 000.

10 citations

Journal ArticleDOI
TL;DR: In this paper , a solid-state 3D range imager based on the pulsed time-of-flight method is presented, which uses block-based segmented illumination in the transmitter realized with a 16-element common anode laser diode bar.
Abstract: Full realization of a solid-state 3-D range imager based on the pulsed time-of-flight method is presented. The system uses block-based segmented illumination in the transmitter realized with a 16-element common anode laser diode bar. The receiver is based on a single chip 2-D SPAD/TDC 0.35 μm CMOS array with 32 × 128 SPAD pixels and 257 TDCs. Segmentation of the illumination improves the SNBGR in the detection and results in simpler receiver realization than in the commonly used flood-illumination approach. The system is capable of producing cm-accurate 3-D range images within a FOV of 40° × 10° up to a range of 15 m in normal office lighting at a frame rate of ∼30 fps using a low average illumination power of only 2.6 mW. In background illumination of ∼20 klux, 3-D range images were captured at a distance of ∼13 m using the gated SPAD approach at a frame rate of ∼1 fps.

2 citations


Cited by
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Journal ArticleDOI
TL;DR: A new coarse-fine TDC architecture is proposed by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process, which will improve the linearity further.
Abstract: This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

465 citations

Journal ArticleDOI
TL;DR: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping.
Abstract: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping. At frequencies below 1 MHz, the TDC error integrates to 80 fs (rms) for a dynamic range of 95 dB with no calibration required. The 157 times 258 mum TDC is realized in 0.13 mum CMOS and, depending on the time difference between input edges, consumes 2.2 to 21 mA from a 1.5 V supply.

340 citations

Journal ArticleDOI
TL;DR: A high-precision CMOS time-to-digital converter IC has been designed based on a counter and two-level interpolation realized with stabilized delay lines that reduces the number of delay elements and registers and lowers the power consumption.
Abstract: A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements.

272 citations

Journal ArticleDOI
07 Apr 2011
TL;DR: This paper introduces a fractional-N PLL based on a 1b TDC, achieving jitter of 560fsrms (from 3kHz to 30MHz) at 4.5mW power consumption, even in the worst-case of fractional spur falling within the PLL bandwidth.
Abstract: This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65-nm CMOS process. It achieves - 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 fsrms (integrated from 3 kHz to 30 MHz), even in the worst-case of a -42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25-Mb/s data rate.

221 citations

Journal ArticleDOI
TL;DR: In this article, the authors present a CMOS imager consisting of 32×32 smart pixels, each one able to detect single photons in the 300-900 nm wavelength range and to perform both photon-counting and photon-timing operations on very fast optical events with faint intensities.
Abstract: We present a CMOS imager consisting of 32×32 smart pixels, each one able to detect single photons in the 300-900 nm wavelength range and to perform both photon-counting and photon-timing operations on very fast optical events with faint intensities. In photon-counting mode, the imager provides photon-number (i.e, intensity) resolved movies of the scene under observation, up to 100 000 frames/s. In photon-timing, the imager provides photon arrival times with 312 ps resolution. The result are videos with either time-resolved (e.g., fluorescence) maps of a sample, or 3-D depth-resolved maps of a target scene. The imager is fabricated in a cost-effective 0.35-μm CMOS technology, automotive certified. Each pixel consists of a single-photon avalanche diode with 30 μm photoactive diameter, coupled to an in-pixel 10-bit time-to-digital converter with 320-ns full-scale range, an INL of 10% LSB and a DNL of 2% LSB. The chip operates in global shutter mode, with full frame times down to 10 μs and just 1-ns conversion time. The reconfigurable imager design enables a broad set of applications, like time-resolved spectroscopy, fluorescence lifetime imaging, diffusive optical tomography, molecular imaging, time-of-flight 3-D ranging and atmospheric layer sensing through LIDAR.

218 citations