The disadvantages of particle swarm optimization (PSO) algorithm are that it is easy to fall into local optimum in high-dimensional space and has a low convergence rate in the iterative process. To deal with these problems, an adaptive particle swarm optimization algorithm based on directed weighted complex network (DWCNPSO) is proposed. Particles can be scattered uniformly over the search space by using the topology of small-world network to initialize the particles position. At the same time, an evolutionary mechanism of the directed dynamic network is employed to make the particles evolve into the scale-free network when the in-degree obeys power-law distribution. In the proposed method, not only the diversity of the algorithm was improved, but also particles’ falling into local optimum was avoided. The simulation results indicate that the proposed algorithm can effectively avoid the premature convergence problem. Compared with other algorithms, the convergence rate is faster.

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An Adaptive Particle Swarm Optimization Algorithm Based on Directed Weighted Complex Network

Recently, much progress has been made on particle swarm optimization (PSO). A number of works have been devoted to analyzing the convergence of the underlying algorithms. Nevertheless, in most cases, rather simplified hypotheses are used. For example, it often assumes that the swarm has only one particle. In addition, more often than not, the variables and the points of attraction are assumed to remain constant throughout the optimization process. In reality, such assumptions are often violated. Moreover, there are no rigorous rates of convergence results available to date for the particle swarm, to the best of our knowledge. In this paper, we consider a general form of PSO algorithms, and analyze asymptotic properties of the algorithms using stochastic approximation methods. We introduce four coefficients and rewrite the PSO procedure as a stochastic approximation type iterative algorithm. Then we analyze its convergence using weak convergence method. It is proved that a suitably scaled sequence of swarms converge to the solution of an ordinary differential equation. We also establish certain stability results. Moreover, convergence rates are ascertained by using weak convergence method. A centered and scaled sequence of the estimation errors is shown to have a diffusion limit.

Analyzing Convergence and Rates of Convergence of Particle Swarm Optimization Algorithms Using Stochastic Approximation Methods

This paper presents fuzzy ${c}$ -means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy ${c}$ -means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a ${k}$ -means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy.

FUZYE: A Fuzzy ${c}$ -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms

State-of-the-art design of analog and radio frequency integrated circuits is often accomplished using sizing optimization. In this paper, an innovative combination of principal component analysis (PCA) and evolutionary computation is used to increase the optimizer's efficiency. The adopted NSGA-II optimization kernel is improved by applying the genetic operators of mutation and crossover on a transformed design-space, obtained from the latest set of solutions (the parents) using PCA. By applying crossover and mutation on variables that are projections of the principal components, the optimization moves more effectively, finding solutions with better performances, in the same amount of time, than the standard NSGA-II optimization kernel. The proposed method was validated in the optimization of two widely used analog circuits, an amplifier and a voltage controlled oscillator, reaching wider solutions sets, and in some cases, solutions sets that can be almost 3 times better in terms of hypervolume.

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel

This paper presents stochastic convergence analysis of particle swarm optimization algorithm involving randomness and applying the results to the Analog RF Circuits to optimize the circuit parameters. In every iteration, each particle position is represented as vector and the standard particle swarm algorithm determined by positive real tipple {w,c 1 ,c 2 }. Comparisons for convergence are presented with respect to fixed tipple {w,c 1 ,c 2 } and random tipple {w,c 1 ,c 2 }. Various results show that the randomness in defining new position to particle leads to better convergence property. Also, exploration and exploitation trade off are discussed with examples. It is demonstrated that each particle undergoes both exploration and exploitation in convergence process; if the randomness in the particle generation is considered. The parameters considered for RF circuit are cutoff frequency, Phase Noise and Signal to Noise Ratio (SNR). Results are compared between both fixed values and random values of parameters in convergence analysis of PSO.

Optimization of Analog RF Circuit parameters using randomness in particle swarm optimization

░ ABSTRACT - Recently, extending the use of memristor technology from memory to computing has received a lot of attention. Memristor-based logic design is a new concept that aims to make computing systems more efficient. Several logic families have emerged, each with its own set of characteristics. In this paper, CMOS-based hybrid memristor-based combinational circuits are designed. Many computational devices require combinational circuits. All of the proposed designs were analysed for power, latency, and transistor count. Cadence Virtuoso is used for simulation of circuits. In this study, we used the VTEAM model to describe the simulated memristor because it is easy to understand and gives accurate results.

Performance Evaluation of Low Power Hybrid Combinational Circuits using Memristor

As technology nodes scale down, many challenges emerge, such as increased leakage current causes high power dissipation, which has become a major issue in low-power circuit design due to transistor size reduction and lower voltage supply. To address these issues, nanotechnology devices are combined with low-power design methods. Spintronics is a new emerging technology that has a high speed, almost no leakage current, and high endurance. This paper proposes a hybrid MTJ-based circuit -XOR/XNOR logic gate and full adder. The hybrid logic gate and hybrid full adder surpass earlier designs in terms of device count, propagation latency, and power consumption. Transient simulations were used to simulate all of the designs using the HSPICE tool 32 nm technology.KeywordsMagnetic tunnel junctionLogic designAdderNon-volatile logic design 

Performance Evaluation of Full Adder Using Magnetic Tunnel Junction

: As CMOS technology shrinks to the deep submicron range, increased power dissipation becomes a big issue. Due to its non-volatility, fast speed, great durability, CMOS compatibility, and low power consumption, the Spin transfer torque (STT) switching mechanism based on Magnetic tunnel Junction (MTJ) is widely regarded as one of the most promising spintronic devices for the post-CMOS era. The research presented here proposes a novel Arithmetic Logic Unit (ALU) that makes use of Spin Hall E ff ect (SHE) to aid with STT / MTJ. In this study, we use SHE-assisted STT logic to create a Hybrid Full Adder and three other logics (AND, OR, and XOR). The proposed logics are then used to create an adder circuit, which is used to create an Arithmetic Logic Unit (ALU). A comparison of each of the proposed designs to the DPTL − C 2 MOS − ALU and P-MALU has been performed. The simulation findings show that the proposed designs outperform competing ALU designs, with a 28% reduction in power consumption and a corresponding reduction in latency. For circuit simulation in 45nm technology, the Cadence Virtuoso tool is employed.

https://journal.uob.edu.bh:443/bitstream/123456789/4865/3/IJCDS140110.pdf

Jyoti Garg

Papers

Optimization of Analog RF Circuit parameters using randomness in particle swarm optimization

Performance Evaluation of Low Power Hybrid Combinational Circuits using Memristor

Performance Evaluation of Full Adder Using Magnetic Tunnel Junction

Design of Low Power Arithmetic logic unit using SHE assisted STT / MTJ