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Jyoti Kiron Bhardwaj

Bio: Jyoti Kiron Bhardwaj is an academic researcher. The author has contributed to research in topics: Etching (microfabrication) & Reactive-ion etching. The author has an hindex of 9, co-authored 18 publications receiving 736 citations.

Papers
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Patent
28 Jul 1997
TL;DR: In this article, a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition is described.
Abstract: This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

250 citations

Journal ArticleDOI
TL;DR: The STS Advanced Silicon Etch (ASE) process as mentioned in this paper is one of the state-of-the-art techniques for high etch rate with good profile/CD control, achieving a photoresist of 150:1 with Si etch rates up to 7 μm/min.
Abstract: In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, ASE™, process satisfies the demanding requirements of the industry. Typically, highly anisotropic, high aspect ratios profiles with fine CD control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 7 μm/min are achievable. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASE™ process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

200 citations

Patent
08 Feb 1999
TL;DR: In this paper, a method and apparatus for etching a substrate is described, which comprises the steps of etching the substrate or alternately etching and depositing a passivation layer.
Abstract: There is disclosed a method and apparatus for etching a substrate. The method comprises the steps of etching a substrate or alternately etching and depositing a passivation layer. A bias frequency, which may be pulsed, may be applied to the substrate and may be at or below the ion plasma frequency.

118 citations

Journal ArticleDOI
TL;DR: In this article, the STS Advanced Silicon Etch (ASETM) process satisfies the demanding requirements of the industry, typically high aspect ratios profiles with fine CD (critical dimension) control are required.
Abstract: In the ongoing enhancement of MEMS applications, the STS Advanced Silicon Etch, (ASETM). process satisfies the demanding requirements of the industry. Typically, highly anisotropic. high aspect ratios profiles with fine CD (critical dimension) control are required. Selectivities to photoresist of 150:1 with Si etch rates of up to 10μm/min are demonstrated. Applications range from shallow etched optical devices to through wafer membrane etches. This paper details some of the fundamental trends of the ASETM process and goes on to discuss how the process has been enhanced to meet product specifications. Parameter ramping is a powerful technique used to achieve the often-conflicting requirements of high etch rate with good profile/CD control. The results are presented in this paper.

35 citations

Patent
28 Jul 1997
TL;DR: In this article, a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition is described.
Abstract: of EP0822582This invention relates to methods for treatment of semiconductor substrates and in particular a method of etching a trench in a semiconductor substrate in a reactor chamber using alternatively reactive ion etching and depositing a passivation layer by chemical vapour deposition, wherein one or more of the following parameters: gas flow rates, chamber pressure, plasma power, substrate bias, etch rate, deposition rate, cycle time and etching/deposition ratio vary with time.

27 citations


Cited by
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Journal ArticleDOI
TL;DR: In this paper, the etch rates of 53 materials that are used or potentially can be used or in the fabrication of microelectromechanical systems and integrated circuits were prepared.
Abstract: Samples of 53 materials that are used or potentially can be used or in the fabrication of microelectromechanical systems and integrated circuits were prepared: single-crystal silicon with two doping levels, polycrystalline silicon with two doping levels, polycrystalline germanium, polycrystalline SiGe, graphite, fused quartz, Pyrex 7740, nine other preparations of silicon dioxide, four preparations of silicon nitride, sapphire, two preparations of aluminum oxide, aluminum, Al/2%Si, titanium, vanadium, niobium, two preparations of tantalum, two preparations of chromium, Cr on Au, molybdenum, tungsten, nickel, palladium, platinum, copper, silver, gold, 10 Ti/90 W, 80 Ni/20 Cr, TiN, four types of photoresist, resist pen, Parylene-C, and spin-on polyimide. Selected samples were etched in 35 different etches: isotropic silicon etchant, potassium hydroxide, 10:1 HF, 5:1 BHF, Pad Etch 4, hot phosphoric acid, Aluminum Etchant Type A, titanium wet etchant, CR-7 chromium etchant, CR-14 chromium etchant, molybdenum etchant, warm hydrogen peroxide, Copper Etchant Type CE-200, Copper Etchant APS 100, dilute aqua regia, AU-5 gold etchant, Nichrome Etchant TFN, hot sulfuric+phosphoric acids, Piranha, Microstrip 2001, acetone, methanol, isopropanol, xenon difluoride, HF+H/sub 2/O vapor, oxygen plasma, two deep reactive ion etch recipes with two different types of wafer clamping, SF/sub 6/ plasma, SF/sub 6/+O/sub 2/ plasma, CF/sub 4/ plasma, CF/sub 4/+O/sub 2/ plasma, and argon ion milling. The etch rates of 620 combinations of these were measured. The etch rates of thermal oxide in different dilutions of HF and BHF are also reported. Sample preparation and information about the etches is given.

1,256 citations

Journal ArticleDOI
TL;DR: High aspect ratio (HAR) silicon etch is reviewed in this paper, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies.
Abstract: High aspect ratio (HAR) silicon etch is reviewed, including commonly used terms, history, main applications, different technological methods, critical challenges, and main theories of the technologies. Chronologically, HAR silicon etch has been conducted using wet etch in solution, reactive ion etch (RIE) in low density plasma, single-step etch at cryogenic conditions in inductively coupled plasma (ICP) combined with RIE, time-multiplexed deep silicon etch in ICP-RIE configuration reactor, and single-step etch in high density plasma at room or near room temperature. Key specifications are HAR, high etch rate, good trench sidewall profile with smooth surface, low aspect ratio dependent etch, and low etch loading effects. Till now, time-multiplexed etch process is a popular industrial practice but the intrinsic scalloped profile of a time-multiplexed etch process, resulting from alternating between passivation and etch, poses a challenge. Previously, HAR silicon etch was an application associated primarily with microelectromechanical systems. In recent years, through-silicon-via (TSV) etch applications for three-dimensional integrated circuit stacking technology has spurred research and development of this enabling technology. This potential large scale application requires HAR etch with high and stable throughput, controllable profile and surface properties, and low costs.

598 citations

Patent
07 Apr 2005
TL;DR: In this article, a method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS devices from contamination, physical contact, or other deleterious external events.
Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

391 citations

Journal ArticleDOI
TL;DR: In this paper, a review of surface tension-powered self-assembly of microstructures is presented, and the demonstrated fabrication processes for accurately determining the assembled shape are discussed, and limits on accuracy and structural distortion are considered.
Abstract: Because of the low dimensional power of its force scaling law, surface tension is appropriate for carrying out reshaping and assembly in the microstructure size domain. This paper reviews work on surface tension powered self-assembly of microstructures. The existing theoretical approaches for rotational assembly are unified. The demonstrated fabrication processes are compared. Mechanisms for accurately determining the assembled shape are discussed, and the limits on accuracy and structural distortion are considered. Applications in optics, electronics and mechanics are described. More complex operations (including the combination of self-assembly and self-organization) are also reviewed.

373 citations

Patent
Zhisong Huang1, Jose Tong Sam1, Eric Lenz1, Rajinder Dhindsa1, Reza Sadjadi1 
22 Apr 2005
TL;DR: In this paper, a gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma-processing apparatus is provided, which can include a gas supply section, a flow control section and a switching section.
Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows. The switching section preferably includes fast switching valves operable to quickly open and close to allow fast switching of the first and second gases, preferably without the occurrence of undesirable pressure surges or flow instabilities in the flow of either gas.

346 citations