K. Batri

Bio: K. Batri is an academic researcher from PSNA College of Engineering and Technology. The author has contributed to research in topics: Leakage (electronics) & Subthreshold conduction. The author has an hindex of 1, co-authored 2 publications receiving 1 citations.

An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits

Abstract: Leakage current has a large impact in the performance of a system. Dominant component of the leakage current is the subthreshold leakage. One of the most sophisticated techniques for reducing leakage current is the transistor stack. Leakage current primarily depends upon the input vectors applied to the circuit. It is possible to demote the leakage current further with the usage of ‘IVC’. If it is possible to control this input vectors means leakage current can be reduced to a greater extent. A number of algorithms already exist to sort out this input vectors, but due to their exhaustive search nature they becomes ineffective. This paper propose an algorithm which focus on the best possible combination of the input vector that reduce the leakage current without trying for all the possible 2 k combinations. The problem can be treated as NP-Complete. Fan-out is not included in the algorithm since it is an independent factor of leakage current. The proposed algorithm precisely produces the input vector which gives the minimum leakage and shows a greater optimization in terms of time complexity and space complexity.

Coignof vantage of Transistor Stack and Input Vector Control Method in Leakage Current Reduction

Abstract: Leakage current has become a regime in deep sub micrometer circuits. When we move from one technology generation to another technology generation leakage current component is increasing. Out of the total power dissipation majority is the leakage power. The dominant component of leakage power is sub threshold leakage current. Minimizing leakage current is very important in battery powered applications since the leakage drains the battery when circuit is idle. In this paper a survey is done in such a manner so as to outline what so far has done to reduce the leakage power. The paper is organized in such manner that it gives a brief description about standby leakage mechanisms, various standby leakage reduction techniques and what all are the existing technique’s available.

Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits

Abstract: Low power consumption is the ultimate goal of the circuit designers of any application and specifically, the life time of event-driven nature of low duty cycle applications like Wireless Sensor Networks (WSN) relies on the design of power-stringent battery-operated devices. At all the hierarchical level of the sensor nodes, low duty cycling is the practicing solution in saving the unwanted power consumption. However, the rapid power squanderer at the sleep state of the circuit is the subthreshold leakage. The exact saving of the leakage can be done by suppressing the short-channel effects of the transistors only at the circuit-level and the two techniques Modified Power Gating (MPG) and Short-pulse POwer Gated Approach (SPOGA, hereafter called as SPOGA_old) are proposed and implemented in the combinational circuits in the previous works of the research. In spite of good subthreshold leakage reduction, the limitations of the proposed techniques are loading effect, state-retention and leakage estimation method. In order to provide an efficient sleep state subthreshold leakage reduction in combinational circuits of low duty cycle application, the limitations are addressed with a revisited design of SPOGA_old, called as SPOGA technique. The illustration of the proposed SPOGA technique with CMOS inverter is done using Cadence GPDK090. From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.