K. Bernstein

Bio: K. Bernstein is an academic researcher. The author has contributed to research in topics: IBM. The author has an hindex of 1, co-authored 1 publications receiving 218 citations.

Techniques for Design and Implementation of Secure Reconfigurable PUFs

Abstract: Physically unclonable functions (PUFs) provide a basis for many security and digital rights management protocols. PUF-based security approaches have numerous comparative strengths with respect to traditional cryptography-based techniques, including resilience against physical and side channel attacks and suitability for lightweight protocols. However, classical delay-based PUF structures have a number of drawbacks including susceptibility to guessing, reverse engineering, and emulation attacks, as well as sensitivity to operational and environmental variations.To address these limitations, we have developed a new set of techniques for FPGA-based PUF design and implementation. We demonstrate how reconfigurability can be exploited to eliminate the stated PUF limitations. We also show how FPGA-based PUFs can be used for privacy protection. Furthermore, reconfigurability enables the introduction of new techniques for PUF testing. The effectiveness of all the proposed techniques is validated using extensive implementations, simulations, and statistical analysis.

Hardware-Based Public-Key Cryptography with Public Physically Unclonable Functions

Abstract: A physically unclonable function (PUF) is a multiple-input, multiple-output, large entropy physical system that is unreproducible due to its structural complexity A public physically unclonable function (PPUF) is a PUF that is created so that its simulation is feasible but requires very large time even when ample computational resources are available Using PPUFs, we have developed conceptually new secret key exchange and public key protocols that are resilient against physical and side channel attacks and do not employ unproven mathematical conjectures Judicious use of PPUF hardware sharing, parallelism, and provably correct partial simulation enables 1016 advantage of communicating parties over an attacker, requiring over 500 of years of computation even if the attacker uses all global computation resources

Modeling Process Variability in Scaled CMOS Technology

Abstract: Process variability has become a critical issue in scaled CMOS design. This article provides a comprehensive view on the predominant variation sources in sub-90-nm devices, their impact on device and circuit performance, and various modeling approaches for statistical circuit analysis.

A Variation-Tolerant Sub-200 mV 6-T

Abstract: In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. We first use detailed simulations to explore the chal- lenges of ultra-low-voltagememorydesign witha specificemphasis on the implications of variability. We then propose a single-ended 6-T SRAM design with a gated-feedback write-assist that remains robust deep in the subthreshold regime. Measurements of a test chip show that the proposed memory architecture functions from 1.2 V down to 193 mV and provides a 36% improvement in energy consumption over the previously proposed multiplexer-based subthreshold SRAM designs while using only half the area. Ad- justable footers and headers are introduced, as well as body bias techniques to extend voltage scaling limits.

Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach

Abstract: We have developed a methodology for unique identification of integrated circuits (ICs) that addresses untrusted fabrication and other security problems. The new method leverages nondestructive gate-level characterization of ICs post-manufacturing, revealing the hidden and unclonable uniqueness of each IC. The IC characterization uses the externally measured leakage currents for multiple input vectors. We have derived several optimization techniques for gate-level characterization. The probability of collision of IDs in presence of intra- and inter-chip correlations is computed. We also introduce a number of novel security and authentication protocols, such as hardware metering , challenge-based authentication and prevention of software piracy , that leverage the extraction of a unique ID for each IC. Experimental evaluations of the proposed approach on a large set of benchmark examples reveals its effectiveness even in presence of measurement errors.