K. Chatty

Bio: K. Chatty is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Thyristor & Electrostatic discharge. The author has an hindex of 1, co-authored 1 publications receiving 45 citations.

Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies

Abstract: The authors compare a number of promising SCR-based ESD protection devices in 90nm and 65nm CMOS technologies implemented with a consistent layout. The devices are evaluated using ESD metrics such as trigger voltage and current, on-resistance, failure current, turn-on time and DC leakage current. The authors also report that SCR turn-on time is highly dependent on the amplitude of the applied pulse.

ESD Design for Analog Circuits

Abstract: Conductivity Modulation in Semiconductor Structures Under Breakdown and Injection.- Standard and ESD Devices in Integrated Process Technologies.- ESD Clamps.- ESD Network Design Principles.- ESD Design for Signal Path Analog.- Power Management Circuits' ESD Protection.- System-Level and Discrete Components ESD.

Investigation of voltage overshoots in diode triggered silicon controlled rectifiers (DTSCRs) under very fast transmission line pulsing (VFTLP)

Abstract: Overshoot voltages during VFTLP testing of DTSCRs are investigated. The DTSCRs in a 65nm process turn on at approximately 500ps. The overshoot voltages from DTSCRs are shown to cause gate oxide failures when gate oxide monitors were added in parallel to DTSCR ESD devices. Scaling trends show DTSCRs turning on at approximately 150ps when technologies are scaled down to the 32nm node.

Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

Abstract: SCRs have been playing an increasingly significant role in ESD protection for CMOS technologies. A major challenge is to develop effective compact simulation models for these devices valid under ESD stress conditions. A simple macro modeling approach is presented for SPICE simulation of LVTSCR devices. The method uses advanced standard BJT and MOS models such as BSIM4 and Mextram. The simulation results have been verified using VFTLP and standard TLP measurements. The method provides a practical simulation tool for ESD protection circuits using LVTSCRs.

Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

Abstract: An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.

Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process

Abstract: A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the power-rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design.