We introduce the 2D counterpart of layered black phosphorus, which we call phosphorene, as an unexplored p-type semiconducting material. Same as graphene and MoS2, single-layer phosphorene is flexible and can be mechanically exfoliated. We find phosphorene to be stable and, unlike graphene, to have an inherent, direct, and appreciable band gap. Our ab initio calculations indicate that the band gap is direct, depends on the number of layers and the in-layer strain, and is significantly larger than the bulk value of 0.31–0.36 eV. The observed photoluminescence peak of single-layer phosphorene in the visible optical range confirms that the band gap is larger than that of the bulk system. Our transport studies indicate a hole mobility that reflects the structural anisotropy of phosphorene and complements n-type MoS2. At room temperature, our few-layer phosphorene field-effect transistors with 1.0 μm channel length display a high on-current of 194 mA/mm, a high hole field-effect mobility of 286 cm2/V·s, and an...

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Phosphorene: An Unexplored 2D Semiconductor with a High Hole Mobility

Graphene’s success has shown that it is possible to create stable, single and few-atom-thick layers of van der Waals materials, and also that these materials can exhibit fascinating and technologically useful properties. Here we review the state-of-the-art of 2D materials beyond graphene. Initially, we will outline the different chemical classes of 2D materials and discuss the various strategies to prepare single-layer, few-layer, and multilayer assembly materials in solution, on substrates, and on the wafer scale. Additionally, we present an experimental guide for identifying and characterizing single-layer-thick materials, as well as outlining emerging techniques that yield both local and global information. We describe the differences that occur in the electronic structure between the bulk and the single layer and discuss various methods of tuning their electronic properties by manipulating the surface. Finally, we highlight the properties and advantages of single-, few-, and many-layer 2D materials in...

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Progress, Challenges, and Opportunities in Two-Dimensional Materials Beyond Graphene

Preceding the current interest in layered materials for electronic applications, research in the 1960's found that black phosphorus combines high carrier mobility with a fundamental band gap. We introduce its counterpart, dubbed few-layer phosphorene, as a new 2D p-type material. Same as graphene and MoS2, phosphorene is flexible and can be mechanically exfoliated. We find phosphorene to be stable and, unlike graphene, to have an inherent, direct and appreciable band-gap that depends on the number of layers. Our transport studies indicate a carrier mobility that reflects its structural anisotropy and is superior to MoS2. At room temperature, our phosphorene field-effect transistors with 1.0 um channel length display a high on-current of 194 mA/mm, a high hole field-effect mobility of 286 cm2/Vs, and an on/off ratio up to 1E4. We demonstrate the possibility of phosphorene integration by constructing the first 2D CMOS inverter of phosphorene PMOS and MoS2 NMOS transistors.

Phosphorene: A New 2D Material with High Carrier Mobility

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

We introduce the 2D counterpart of layered black phosphorus, which we call phosphorene, as an unexplored p-type semiconducting material. Same as graphene and MoS2, single-layer phosphorene is flexible and can be mechanically exfoliated. We find phosphorenetobestableand,unlikegraphene,tohaveaninherent, direct, and appreciable band gap. Our ab initio calculations indicate thatthebandgapisdirect,dependsonthenumberoflayersandthe in-layer strain, and is significantly larger than the bulk value of 0.31� 0.36 eV. The observed photoluminescence peak of single-layer phosphorene in the visible optical range confirms that the band gap is larger than that of the bulk system. Our transport studies indicate a hole mobility that reflects the structuralanisotropyofphosphoreneandcomplementsn-typeMoS2.Atroomtemperature,ourfew-layerphosphorene field-effecttransistorswith1.0 μm channellengthdisplayahighon-currentof194mA/mm,ahighhole field-effectmobilityof286cm 2 /V 3 s,andanon/offratioofupto10 4 .Wedemonstrate the possibility of phosphorene integration by constructing a 2D CMOS inverter consisting of phosphorene PMOS and MoS2 NMOS transistors.

Phosphorene: An Unexplored 2D Semiconductor with a High Hole

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Scaling the Si MOSFET: from bulk to SOI to bulk

We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics. >

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region. >

89-GHz f/sub T/ room-temperature silicon MOSFETs

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics. >

High performance 0.1- mu m room temperature Si MOSFETs

An ideal device structure for integrating bipolar and CMOS is reported in this paper. Both the vertical npn and MOS devices have new non-overlapping super self-aligned structures. With a single 5V supply, averaged per stage delay of 82ps and 125ps have been measured for 0.6µm and 0.85µm (L eff ) CMOS ring oscillators. Bipolar transistors have also been fabricated with a nominal current gain of 100.

K.F. Lee

Papers

Scaling the Si MOSFET: from bulk to SOI to bulk

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

89-GHz f/sub T/ room-temperature silicon MOSFETs

High performance 0.1- mu m room temperature Si MOSFETs

A high speed super self-aligned bipolar-CMOS technology