K.H. Zaininger

Bio: K.H. Zaininger is an academic researcher from Princeton University. The author has contributed to research in topics: Differential capacitance & Wafer. The author has an hindex of 2, co-authored 2 publications receiving 195 citations.

Limitations of the MOS capacitance method for the determination of semiconductor surface properties

Abstract: For the use of the MOS capacitance method in the study of surface properties, various approximations and assumptions, of a purely conceptual and of an experimental nature, are usually made. These are not always justified. In this paper the applicability of this capacitance method for surface studies is examined critically. It is shown that this method is limited in its applicability and accuracy, and that, in most cases, it yields only the gross features of the surface states. If there are traps distributed spatially throughout the oxide, only an effective surface state distribution can be found, and this effective distribution may be interpreted ambiguously as due either to traps right at the interface, throughout the oxide, or both. Because the MOS capacitance consists essentially of the oxide capacitance in series with the semiconductor capacitances there is a practical lower limit on the magnitude of the semiconductor capacitance which can be measured. Together with difficulties in interpreting measurements in the inversion layer regime, this leads to a restriction on that portion of the forbidden gap in which states may be investigated. MOS capacitors, produced by thermal oxidation of silicon in either wet or dry oxygen, were examined by this method. It was found that, within experimental accuracy, and within the range of surface potential that can be covered by these measurements, the total number of occupied traps usually varies linearly with surface potential if it is assumed that all the traps are located right at the interface. However, these results can also be explained if it is assumed that the oxide contains a high density of low lying trap sites which are essentially uniformly distributed spatially throughout the oxide. In some specimens a monoenergetic trap level 0.7 eV below the conduction band and located at the interface was found.

Radiation resistance of Al 2 O 3 MOS devices

Abstract: Integrated circuits employing MOS devices will play a vital role in tomorrow's civilian and military electronics if their degradation in a radiation environment can be eliminated. One possible approach toward alleviating radiation effects in MOS devices is to use a material with a defect structure that does not allow predominant trapping of either holes or electrons as a gate insulator. This has been done by constructing MOS devices with plasma-grown aluminum oxide. The Al 2 O 3 films are formed by first depositing aluminum on freshly cleaned and properly prepared silicon wafers. Subsequently this aluminum is oxidized in an oxygen plasma and device fabrication is then completed. The devices have excellent characteristics and stability, and their fabrication is not restricted by the conditions of the ultra-clean procedures necessary for SiO 2 -Si devices. Exposure to 1-MeV electron bombardment at various fluence levels and bombardment-bias conditions shows that these structures possess remarkable radiation resistance. Up to a fluence of 1 × 1013e/cm2, under positive or negative bias, no oxide charge buildup or interface state generation is detectable. Above that fluence, only small shifts are observed. This indicates that an order of magnitude improvement in device hardening can be achieved by the use of this material.

The si-sio, interface – electrical properties as determined by the metal-insulator-silicon conductance technique

Abstract: Measurements of the equivalent parallel conductance of metal-insulator-semiconductor (MIS) capacitors are shown to give more detailed and accurate information about interface states than capacitance measurements. Experimental techniques and methods of analysis are described. From the results of the conductance technique, a realistic characterization of the Si–SiO 2 interface is developed. Salient features are: A continuum of states is found across the band gap of the silicon. Capture cross sections for holes and electrons are independent of energy over large portions of the band gap. The surface potential is subject to statistical fluctuations arising from various sources. The dominant contribution in the samples measured arises from a random distribution of surface charge. The fluctuating surface potential causes a dispersion of interface state time constants in the depletion region. In the weak inversion region the dispersion is eliminated by interaction between interface states and the minority carrier band. A single time constant results. From the experimentally established facts, equivalent circuits accurately describing the measurements are constructed.

Surface states at steam-grown silicon-silicon dioxide interfaces

Abstract: A method of determining the energy distribution of surface states at silicon-silicon dioxide interfaces by using low-frequency differential capacitance measurements of MOS structures is described. Low-frequency measurements make it possible to determine the silicon surface potential as a function of MOS voltage directly from the experimental data without requiring knowledge of the Si doping profile. No graphical differentiations are required to determine the surface state density from the experimental curves, and errors introduced by uncertainties in the silicon doping density are reduced. Also, it is shown that the measurements can be used to determine the relative lateral uniformity in the characteristics of the oxide and interface under the MOS field plate. Nonuniformities can result in large errors in the surface-state density derived from MOS capacitance measurements. Measurements are presented and interpreted for both n- and p-type silicon samples prepared by bias-growing the oxide in steam.

A quasi-static technique for MOS C-V and surface state measurements

Abstract: A quasi-static technique is discussed for obtaining the ‘low frequency’ thermal equilibrium MOS capacitance-voltage characteristics The method is based on a measurement of the MOS charging current in response to a linear voltage ramp, so that the charging current is directly proportional to the incremental MOS capacitance With this technique, surface potential and the surface state density can be obtained relatively simply and over a large part of the energy gap on a single sample, while also providing a direct test for the presence of gross nonuniformities in MOS structures This method has been used to determine the surface state distribution at the interface of a bias grown steam oxide and 10 ω-cm n -type silicon, and the results are compared with composite measurements using the conductance technique for a similar interface The sensitivity for surface state density measurements is estimated to be of the order of 10 10 states per cm 2 eV near mid-gap for 10 ω-cm silicon and improves with decreasing doping density Some applications and limitations are also briefly discussed

Substrate crosstalk reduction using SOI technology

Abstract: This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.