K. Hara

Bio: K. Hara is an academic researcher from Applied Science Private University. The author has contributed to research in topics: Detector & Microstrip. The author has an hindex of 4, co-authored 5 publications receiving 70 citations.

Radiation Resistance of SOI Pixel Devices Fabricated With OKI 0.15 $\mu {\rm m}$ FD-SOI Technology

Abstract: Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32times32 matrix with 20 mum times 20 mum pixels were irradiated with 60Co gamma's up to 0.60 MGy and with 70-MeV protons up to 9.3times10 60Co p/cm2. The performance characterization was made on the electronics part and as a photon detector from the response to reset signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation of the characteristics changes in the transistors was separately carried out using transistor test structures to which a wider range of irradiation, from 0.12 kGy to 5.1 MGy, was made with 60Co gamma's.

Monolithic Pixel Detector in a 0.15 μm SOI Technology

Abstract: We describe a new pixel detector development project using a 0.15 μm fully-depleted CMOS SOI (silicon-on-insulator) technology. Additional processing steps for creating substrate implants and contacts to form sensor and electrode connections were developed for this SOI process. A diode test element group and several test chips have been fabricated and evaluated. The pixel detectors are successfully operated and first images are taken and sensibility to β-rays is confirmed. Back gate effects on the top circuits are observed and discussed.

Development of Radiation Hard ${\rm N}^{+}$ -on-P Silicon Microstrip Sensors for Super LHC

Abstract: Radiation tolerance up to 1015 1-MeV neq/cm2 is required for the silicon microstrip sensors to be operated at the Super LHC experiment. As a candidate for such sensors, we are investigating non-inverting n+-on-p sensors. We manufactured sample sensors of 1 times 1 cm in 4" and 6" processes with implementing different interstrip electrical isolation structures. Industrial high resistive p-type wafers from FZ and MCZ growth are tested. They are different in crystal orientations lang100rang and lang111rang with different wafer resistivities. The sensors were irradiated with 70-MeV protons and characterized in views of the leakage current increase, noise figures, electrical strip isolation, full depletion voltage evolution, and charge collection efficiency.

SOI pixel developments in a 0.15μm technology

Abstract: While the SOI (silicon-on-insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and low-power applications Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology In 2005 we started Si pixel R&D with OKI Electric Ind Co, Ltd which is the first market supplier of fully-depleted SOI products We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 015mm FD-SOI CMOS process We have preformed two multi project wafer (MPW) runs using this SOI process We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories Features of these SOI devices and experiences with SOI pixel development are presented

First Results of 0.15_m CMOS SOI Pixel Detector

Abstract: Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda IPNS, High Energy Accelerator Reserach Organization (KEK), Ibaraki 305-0801, JAPAN H. Ikeda ISAS, Japan Aerospace Exploration Agency (JAXA), Kanagawa 229-8510, JAPAN K. Hara Institute of Pure and Applied Science, University of Tsukuba, Ibaraki 305-8571, JAPAN H. Ishino Department of Physics, Tokyo Institute of Technology, Tokyo 152-8551, JAPAN T. Kawasaki Graduate School of Science and Technology, Niigata University, Niigata 950-2181, JAPAN E. Martin, G. Varner Department of Physics and Astronomy, University of Hawaii, Honolulu, HI 86822, USA H. Tajima Stanford Linear Accelerator Center, Stanford, CA 94307-4349, USA M. Ohno, K. Fukuda, H. Komatsubara, J. Ida Oki Electric Industory Co. Ltd., Tokyo 193-8550, JAPAN

Development of SOI pixel process technology

Abstract: A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.

Development of n-on-p silicon sensors for very high radiation environments

Abstract: We have developed a novel and highly radiation-tolerant n-in-p silicon microstrip sensor for very high radiation environments such as in the Super Large Hadron Collider. The sensors are designed for a fluence of 1×1015 neq/cm2 and are fabricated from p-type, FZ, 6 in. (150 mm) wafers onto which we lay out a single 9.75 cm×9.75 cm large-area sensor and several 1 cm×1 cm miniature sensors with various n-strip isolation structures. By evaluating the sensors both pre- and post-irradiation by protons and neutrons, we find that the full depletion voltage evolves to approximately 800 V and that the n-strip isolation depends on the p+ concentration. In addition, we characterize the interstrip resistance, interstrip capacitance and the punch-through-protection (PTP) voltage. The first fabrication batch allowed us to identify the weak spots in the PTP and the stereo strip layouts. By understanding the source of the weakness, the mask was modified accordingly. After modification, the follow-up fabrication batches and the latest fabrication of about 30 main sensors and associated miniature sensors have shown good performance, with no sign of microdischarge up to 1000 V.

Monolithic Active Pixel Sensors (MAPS) in a Quadruple Well Technology for Nearly 100% Fill Factor and Full CMOS Pixels.

Abstract: In this paper we present a novel, quadruple well process developed in a modern 0.18 mm CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50 mm pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

Monolithic Active Pixel Sensors (MAPS) in a quadruple well technology for nearly 100% fill factor and full CMOS pixels

Abstract: In this paper we present a novel, quadruple well process developed in a modern 0.18mu CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50mu pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.

First Performance Evaluation of an X-Ray SOI Pixel Sensor for Imaging Spectroscopy and Intra-Pixel Trigger

Abstract: We have been developing a monolithic active pixel sensor with the 0.2 μm Silicon-On-Insulator (SOI) CMOS technology, called SOIPIX, for the wide-band X-ray imaging spectroscopy on future astronomical satellites. SOIPIX includes a thin CMOS-readout-array layer and a thick high-resistivity Si-sensor layer stacked vertically on a single chip. This arrangement allows for fast and intelligent readout circuitries on-chip, providing advantages over the charge-coupled device (CCD). We have designed and built a new SOIPIX prototype XRPIX1 for X-ray detection. XRPIX1 implements a correlated double sampling (CDS) readout circuit in each pixel to suppress the reset noise. We obtained an energy resolution of full width at half maximum of 1.2 keV (5.4%) at 22 keV with a chip having a 147 μm sensor depletion at a back bias of 100 V cooled to -50°C. Moreover, XRPIX1 offers intra-pixel hit trigger (timing) and two-dimensional hit-pattern (position) outputs. We also confirmed the trigger capability by irradiating a single pixel with laser light.