K. Jagannadha Naidu

Bio: K. Jagannadha Naidu is an academic researcher from VIT University. The author has contributed to research in topics: Ćuk converter & Switched capacitor. The author has an hindex of 3, co-authored 10 publications receiving 22 citations.

Partial Reconfigurable Implementation of IEEE802.11g OFDM

Abstract: Today's mobile networks are moving towards creating base stations and mobile stations that are compatible with many standards simultaneously. One way of achieving it is to reconfigure and time multiplex the processing resources based on the present necessity. Field Programmable Gate Arrays have become one of the best choices for implementing digital signal processing and Software Defined Radio platforms due to advancements in VLSI over the past few decades. Partial Reconfiguration has regained its importance in the last decade and is the one of the best methodologies to implement an Software Defined Radio. This paper presents an implementation of physical layer specifications of IEEE 802.11g using dynamic partial reconfiguration on FPGA. The Orthogonal Frequency Division Multiplexing (OFDM) Physical layer is implemented with various encoding and modulation schemes to achieve different data rates. The design has been implemented in Xilinx Virtex-5 board.

A low power and high speed 10 transistor full adder using multi threshold technique

Abstract: An adder is one of the main components in many digital devices, DSP processors, etc. Leakage power reduction and area have become important factors in designing recent VLSI circuits. As the technology is constantly scaling down, threshold voltage of transistors is also reduced, thereby making the static power dissipation high. In this paper a low power 10T full adder is designed in 45 nm complementary pass transistor technology. Power dissipation and delay are compared with the conventional 28 transistor full adder, proposed 10 transistor full adder, Multi Threshold CMOS (MTCMOS) based 28 transistor full adder and proposed Multi Threshold based 10 transistor full adder. Compared to the conventional 28 transistor full adder, the proposed design shows power dissipation is reduced by 99.528% and Power Delay Product (PDP) by 99.913%. The proposed circuit reduces the area used by 64% accompanied with high speed of operation.

Design and Verification of Slave Block in Ethernet Management Interface using UVM

Abstract: Objective: Verification of the Slave block in Ethernet Management Interface using UVM. Methodology: Management data input output (MDIO) and Management data clock (MDC) is a two-wire interface used by Ethernet Station Management Entity to configure as well as read status from various PHY devices connected to it. Universal verification methodology is used to verify integrated designs. Verification of the Slave block in Ethernet Management Interface is done through UVM. Findings: Verification environment for the Slave Block in Ethernet Management Interface is built using UVM. 94.44% functional coverage and 97.96 code coverage is achieved. Applications: Ethernet protocol is used in the computer communication.

Implementation of delay and power monitoring schemes to reduce the power consumption

Abstract: As process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold power must be balanced. The exclusive supply voltage control switching makes stable operations. The threshold voltage control successfully maintains a ratio of switching to leakage current and which represents the reduced power consumption. The goal of this paper is to: i) Maintains the optimized body bias conditions. ii) Maintains the best power-delay tradeoff. The results with a 180-nm CMOS device explain that the proposed architecture causes in the successful optimization of power.

On Chip DC-DC Converter with High Switching Frequency and Low Ripple Voltage

Abstract: Objectives: A novel On Chip switched capacitor architecture to produce multiple voltages with high switching frequency and low ripple voltage. Methods: The proposed architecture uses integration of more than one converter topology to produce the scalable output voltage. The converter consists of MOSFET switches and MOS charge-transfer capacitors. The control circuitry was designed completely with digital domain to reduce static power consumed. Findings: The simulation of the scalable DC-DC converter was performed using TSMC 90nm Technology .The maximal efficiency of 80% was achieved for different topologies with 364 MHz switching frequency. Improvements: The load driving capacity of this converter was up to 5uW.

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

Abstract: This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V DD and threshold voltage V TH in active and standby modes. In the active mode, on the basis of delay monitoring results, either V DD control or V TH control is selected to avoid any oscillation problem between them. In V DD control, on the basis of delay monitoring results, V DD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V TH control, on the basis of power monitoring results, V TH is adjusted so as to maintain a certain switching current I SW /leakage current I LEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I SUBTH to substrate current I SUB ) is improved by taking into consideration both the effects of lowering V DD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I SW /I LEAK ratio in the active mode and 2) detect optimum body bias conditions (I SUBTH = I SUB ) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.

Performance Evaluation of IEEE 802.11ac and 802.11n using NS3

Abstract: Objectives: In this paper, the performance parameters in the WLANs are discussed and we evaluate the superior performance of the new IEEE 802.11ac standard with respect to 802.11n. Methods/Analysis: NS3 is an open source network simulator, the latest version of which (ns-3.24.1) has been appended with features to support 802.11ac. Simulations are performed in NS3 to demonstrate the superior performance of the new 802.11ac standard with respect to 802.11n. Features verified are channel bonding, guard interval and MCS while performance is measured with parameters such as jitter, throughput and delay. Findings: IEEE 802.11ac is a Very High Throughput (VHT) WLAN standard that can achieve data rates in the order of 7 Gbps in the 5 GHz band. This has been achieved by enhancing the features in the earlier IEEE 802.11n standard in the MAC and PHY layers. The simulations reveal improvement in throughput, delay and jitter performance with usage of increased bandwidths.

Area Optimization of CMOS Full Adder Design Using 3T XOR

Abstract: GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of area and power consumption of digital circuits. In this design XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also done by reducing supply voltage. In this proposed full adder, the power consumption 4.604µW is achieved and the total area is 144µm2.

ARM-FPGA-based platform for reconfigurable wireless communication systems using partial reconfiguration

Abstract: Today, wireless devices generally feature multiple radio access technologies (LTE, WIFI, WIMAX,...) to handle a rich variety of standards or technologies.These devices should be intelligent and autonomous enough in order to either reach a given level of performance or automatically select the best available wireless technology according to standards availability. On the hardware side, system on chip (SoC) devices integrate processors and field-programmable gate array (FPGA) logic fabrics on the same chip with fast inter-connection. This allows designing software/hardware systems and implementing new techniques and methodologies that greatly improve the performance of communication systems. In these devices, Dynamic partial reconfiguration (DPR) constitutes a well-known technique for reconfiguring only a specific area within the FPGA while other parts continue to operate independently. To evaluate when it is advantageous to perform DPR, adaptive techniques have been proposed. They consist in reconfiguring parts of the system automatically according to specific parameters. In this paper, an intelligent wireless communication system aiming at implementing an adaptive OFDM-based transmitter and performing a vertical handover in heterogeneous networks is presented. An unified physical layer for WIFI-WIMAX networks is also proposed. The system was implemented and tested on a ZedBoard which features a Xilinx Zynq-7000-SoC. The performance of the system is described, and simulation results are presented in order to validate the proposed architecture.

Performance Evaluation for Wavelet based OFDM System effected by CFO over Rayleigh Channel

Abstract: OFDM systems due to its orthogonality factor provides significant spectrum efficiency, robustness to fading and simple cost effective implementation. One of the factors that effects the OFDM system performance is the Carrier Frequency Offset (CFO) that results in the Inter-Carrier Interference (ICI) which causes a degradation of the OFDM system performance. In this paper, a discussion on the performance of Discrete Wavelet Transform (DWT) OFDM and Fourier Transform (FFT) OFDM is done by considering the presence of CFO in both the systems. A comparative study of both the systems is done on the basis of Bit Error Rate (BER) performance these systems show. The system is considered on the basis of improvement in the BER. Simulations conclude that the system that uses wavelet implementation performs better than the conventional OFDM system. The DWT performance even with CFO factors shows considerable improvement in the bit error performance than the FFT based traditional system. Further, the whole simulation is done under the Rayleigh channel, the performance calculated for five practical values of CFO from 0 to 0.2 with step difference of 0.05. The BER performance is simulated using MATLAB software. Further, the whole simulation is done under the Rayleigh channel, the performance calculated for five practical values of CFO from 0 to 0.2 with step difference of 0.05. The DWT based OFDM outperforms the FFT based OFDM for all the values of CFO.