K.-L.J. Wong

Bio: K.-L.J. Wong is an academic researcher from Broadcom. The author has contributed to research in topics: Nyquist ISI criterion & Jitter. The author has an hindex of 1, co-authored 1 publications receiving 43 citations.

Edge and Data Adaptive Equalization of Serial-Link Transceivers

Abstract: Limited channel bandwidth introduces inter-symbol interference (ISI) at both data and edge samples. In addition to the ISI at data samples, ISI at the edge samples (edge ISI) increases the bit error rate (BER) by degrading on the eye diagram and increasing the jitter of the clock and data recovery (CDR). This work proposes a forward FIR equalizer and a decision-feedback equalizer (DFE) that compensate for both data and edge samples. To adapt both the data and edge equalizers, a modified LMS adaptation algorithm is introduced to achieve convergence. A transmitter and receiver are implemented in 0.13 mum and 0.18 mum technologies respectively. The edge ISI is improved by 20% and the jitter is improved by 10% in measurement. The link operates over a 120'' FR4 channel with 24 dB attenuation at Nyquist frequency, and the BER is below 10-14 at 3.6 Gb/s.

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology

Abstract: This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines precisely adjusted by a closed-loop delay controller. The receiver employs a similar 3-tap FIR filter as an equalizer front-end with digital adaptation, and a sub-rate clock and data recovery circuit using majority voting phase detection. The transceiver delivers 40-Gb/s 27-1 PRBS data across a Rogers channel of 20 cm (19-dB loss at 20 GHz) with BER <; 10-12 while consuming a total power of 655 mW.

Power Optimized ADC-Based Serial Link Receiver

Abstract: Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital signal post-processing has drawn growing interest with technology scaling, but power consumption remains among the key issues for such digital receiver in high speed applications. This paper presents an ADC-based receiver that uses a low-gain analog and mixed-mode pre-equalizer in conjunction with non-uniform reference levels for the ADC. The combination compensates for both the frontend non-ideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. The receiver is fabricated in a 65 nm CMOS technology with 10 Gb/s data rate, and has 13 pJ/bit and 10.6 pJ/bit power efficiency for a 29 dB and a 23 dB loss channel respectively.

ADC-based serial I/O receivers

Abstract: Digital receiver frontends have emerged as a possible solution for the next-generation serial I/O receiver design in advanced CMOS technologies The challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs With a power budget of <; 20 mW/Gb/s, the feasibility of an ADC-based receiver is limited by the high-speed analog-to-digital converter (ADC) and complex digital processing in current fabrication technologies In this paper, various designs and architectures for each component of an ADC-based receiver and their performance trade-offs are discussed The design requirement of an ADC and digital processing can be relaxed with the aid of simple mixed-mode circuitry More complex digital processing techniques are becoming feasible with the scaling of CMOS technology However, the improvement from scaling is limited by the substantial leakage current, and the rate of improvement is slowing beyond 32 nm technology node

Split-path equalizer and related methods, devices and systems

Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Design techniques for decision feedback equalisation of multi-giga-bit-per-second serial data links: a state-of-the-art review

Abstract: This study provides a comprehensive review of decision feedback equalisation (DFE) for multi-giga-bit-per-second (Gbps) data links. The state-of-the-art of DFE for multi-Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross-talk and their impact on data transmission are investigated. The fundamentals of both near-end and far-end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi-Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.