An analytical subthreshold current model for metal oxide semiconductor field effect transistors (MOSFETs) with pocket implantation is presented. The model is developed based on considering an averaged localized pileup of channel dopants near the source and drain ends of channel to account for the pocket implantation effect and to derive the channel potential using a pseudo-two-dimensional (2-D) method. This, together with the conventional drift-diffusion theory, leads to the development of a subthreshold current model for pocket-implanted MOS devices. Model verification is carried out using data measured from a set of pocket-implanted NMOSFETs fabricated from a 0.17-/spl mu/m, DRAM process. Very good agreement is obtained between the model calculations and measurement results.

An analytical subthreshold current model for pocket-implanted NMOSFETs

A simple analytical threshold voltage equation for modelling nonuniform MOSFET channel doping is derived, which takes the peak doping concentration and peak location as inputs with a single process-dependent fitting parameter. The model has been verified with extensive numerical simulation results and can be applied to real devices for a wide range of nonuniform doping profiles with a simple, empirical parameter extraction.

Modelling of threshold voltage with non-uniform substrate doping [MOSFET]

This paper presents a compact length-dependent saturation current (Idsat) model for deep-submicron MOSFET’s based on accurate modeling of the threshold voltage (Vth). The proposed unified model has considered all the important two-dimensional (2-D) short-channel effects, such as Vth roll-up and roll-off, drain-induced barrier lowering (DIBL), transverse-field mobility degradation and series resistance. The unique feature of the compact model is its ability to correlate to process variations such as implantation dose and energy. The model is verified with measured Idsat data for various bias conditions and process split-run.

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A Predictive Length-Dependent Saturation Current Model Based on Accurate Threshold Voltage Modeling

As CMOS technology scaling continues, subthreshold leakage current increases dramatically. A significant percentage of the total chip power is due to leakage sources, also known as static power. Accurately estimating static power in early stages of design is an important step for developing power efficient products. Leakage current is an important segment of total supply current, which is used as a means to identify defective chips. Leakage current value is determined by the sum of leakage currents of those transistors that can leak. Setting leakage current value too high or low will result in excessive shipment of defective chips or yield loss because of rejecting good parts, respectively. So it is important to analyse leakage current in circuits in order to reduce theme. Reducing power dissipation is a design goal in devices since excessive power dissipation results in increased packaging and cooling costs as well as potential reliability problems. Our purpose in this work consists in highlighting certain leakage currents by SPICE and MATLAB simulation in submicron structures MOSFET such as the short channel transistor: the BSIM4.we did focus mainly in this study on subthreshold, IGIDL, IDIBL, IOFF, Ion currents.

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Etude Et Simulation Des Courants De Fuites Dans Les Transistors MOS A Canaux Courts

An analytical drain current model is presented for NMOSFETs with pocket implantation. An effective doping concentration derived from the voltage-doping transformation is used to characterize the lateral doping profile of pocket implantation, and subsequently to model the threshold voltage of MOSFETs. Relevant device physics, such as the reverse short-channel effect, velocity saturation, and channel length modification are included in the present model. Moreover, a discrete effective electron mobility model extracted from measured data is incorporated to improve the model accuracy. Hermite interpolation is then applied to describe the drain current behavior in the transition region between the subthreshold and strong inversion regions. Model verifications are carried out using experimental data of MOS devices fabricated from a 0.14-μm DRAM technology.

A comprehensive and analytical drain current model for pocket-implanted NMOSFETs

A compact threshold voltage model is developed for the prediction of deep-submicron MOSFETs scaling characteristic based on comprehensive 2-D device simulation, empirical formulation, and correlation to experimental data. The model incorporates the nonuniformities and nonlinearities from 2-D device physics, relates to process variables, and yet is efficient to use.

K. Loiko

Papers

A predictive semi-analytical threshold voltage model for deep-submicron MOSFET's