K. Mahadeva Bhat

Bio: K. Mahadeva Bhat is an academic researcher from Solid State Physics Laboratory. The author has contributed to research in topics: Ohmic contact & High-electron-mobility transistor. The author has an hindex of 4, co-authored 15 publications receiving 70 citations. Previous affiliations of K. Mahadeva Bhat include University of California, Davis.

Dispersion Free 450-V p GaN-Gated CAVETs With Mg-ion Implanted Blocking Layer

Abstract: In this letter, a GaN-based current aperture vertical electron transistor (CAVET) with a p-type gate layer and an implantation-based current blocking structure is presented. The devices measured showed a breakdown voltage of 450 V and no dispersion. The factors limiting higher breakdown voltages in these devices were carefully studied and discussed. The devices were grown on sapphire and relied on a box-shaped Mg implanted current blocking scheme. This is the first demonstration of an implantation-based CAVET, grown on sapphire blocking of 450 V with respectable on-state characteristics.

Ohmic contacts to pseudomorphic HEMTs with low contact resistance due to enhanced Ge penetration through AlGaAs layers

Abstract: AuGe/Ni ohmic contacts are used as source and drain electrodes of pseudomorphic HEMTs (pHEMTs). High alloying temperatures are generally believed to be necessary to enhance penetration of the alloy materials through the AlGaAs layers in order to establish a very low resistance path for the source–drain currents to access the two-dimensional electron gas (2DEG) layer. Here we have performed alloying experiments in the temperature range of 390–450 °C, and the contact resistance was determined using transfer length method measurements. Germanium diffusion was studied using backside secondary ion mass spectrometry. During our study, we have observed that doping of the channel by germanium is possible even at lower temperatures. But alloying at lower temperatures does not appreciably enhance the concentration throughout the different device layers below the contact pads. Hence, unlike MESFET alloying, higher alloying temperatures are essential for increasing the doping concentration so as to reduce the contact resistance and overcome the resistance of the AlGaAs layers.

MESFET process based planar schottky diode and its application to passive power limiters

Abstract: Design and development of a planar Schottky diode which is process compatible with general planar MESFET process is described here. The device geometry has been designed and optimized keeping in view the applications up to Ku-band. The device was fabricated and characterized to extract the diode model. Two representative application circuits, viz. two types of microwave power limiters were designed, fabricated and tested to show the versatility of the device.

Influence of activation of Si 29+ ion-implantation in GaAs on ohmic contact resistance and electrical performances of MESFETs

Abstract: The active layers of Metal Semiconductor Field Effect Transistors (MESFETs) are obtained by Si29+ ion implantation in GaAs. Implantation was done at 35 keV with a higher dose near the wafer surface for facilitating easier formation of ohmic contacts, and at 180 keV with a lower dose for obtaining the device channel. Post-implantation annealing was carried out in a rapid thermal processor for activating the implants. Very high activation levels of about 60% for the n+ GaAs layer, and 85% for the n-GaAs channel layer were achieved by annealing at 955 °C for 25 s. Activation was characterized using C–V profiling, secondary ion mass spectrometry and by electrical device data of fabricated MESFETs. We attempt an experimental correlation between the ohmic contact resistance (R c) and activation of both the n+ and the channel layer. It was found that very high and simultaneous activation of the n+ and channel layers results in very low contact resistances. The conduction of source-drain current into the channel ...

880 V/ $2.7~\text{m}\Omega\cdot\text{cm}^{\text{2}}$ MIS Gate Trench CAVET on Bulk GaN Substrates

Abstract: In this letter, we report a high-voltage metal-insulator-semiconductor gate trench current aperture vertical electron transistor using metal–organic chemical vapor deposition regrown AlGaN/GaN as the channel and in-situ Si3N4 as the gate dielectric. The device had a high breakdown voltage of 880 V and a low $\text{R}_{\mathrm {on,sp}}$ of $2.7~\text {m}\Omega \cdot \text {cm}^{2}$ . A low hysteresis of ~0.1 V was observed due to the high quality of the in situ Si3N4.

Large-Area In-Situ Oxide, GaN Interlayer-Based Vertical Trench MOSFET (OG-FET)

Abstract: We present a large-area in-situ oxide, GaN interlayer-based vertical trench MOSFET (OG-FET) with a metal organic chemical vapor deposition regrown 10-nm unintentional-doped-GaN interlayer as the channel and 50-nm in-situ Al2O3 as the gate dielectric. The threshold voltage of the device on bulk GaN substrate was 1 V measured at $\text{I}_\mathrm {on}/\text{I}_\mathrm {off}= 10^{7}$ . The OG-FET with an area scaled to 0.2 mm2 demonstrated a breakdown voltage ( $\text{V}_\mathrm {BR}$ ) of 320 V and an on-state resistance ( $\text{R}_\mathrm {on}$ ) of $3.8~\Omega $ (specific on-state resistance: $\text{R}_\mathrm {on,sp}= 7.6\,\,\text{m}\Omega \,\,\cdot $ cm2). For the single unit cell OG-FET from the same sample, $\text{V}_\mathrm {BR}$ was as high as 700 V (measured at $\text{V}_\mathrm {GS}=-10$ V), corresponding to a breakdown electric field of 1.4 MV/cm and $\text{R}_\mathrm {on,sp}$ of 0.98 $\text{m}\Omega ~\cdot $ cm2. On our control sample, which was grown on sapphire substrate, a 1-A current was measured as well. These results show the potential of the OG-FET in power conversion applications.

Development of GaN Vertical Trench-MOSFET With MBE Regrown Channel

Abstract: GaN vertical trench-MOSFETs incorporating molecular beam epitaxy (MBE) regrown channel are developed and investigated. The channel regrowth by MBE prevents repassivation of the p-type GaN body while promising higher channel mobility. Two different designs of the lateral portion of the regrown channel are compared: without or with an n+-GaN buried layer. Without an n+ buried layer, a respectable 600-V breakdown voltage (BV) is measured in the absence of edge termination, indicating a decent critical field strength (>1.6 MV/cm) of the regrown channel. However, the ON-resistance is limited by the highly resistive lateral channel due to Mg incorporation. With an n+ buried layer, the limitation is removed. Excellent ON-current of 130 mA/mm and ON-resistivity of $6.4 ~\rm {m\Omega \cdot cm^{2}}$ are demonstrated. The BV is limited by high source–drain leakage current from the channel due to drain-induced barrier lowering (DIBL) effect. Device analysis together with TCAD simulations points out the major cause for the DIBL effect: the presence of interface charge beyond a critical value ( $\sim 6\times 10^{12}\,\,\rm {cm^{-2}}$ ) at the regrowth interface on etched sidewalls. This paper provides valuable insights into the design of GaN vertical trench-MOSFET with a regrown channel, where simultaneous achievement of low ON-resistivity and high BV is expected in devices with reduced interface charge density and improved channel design to eliminate DIBL.