K. Nummila

Bio: K. Nummila is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Field-effect transistor & High-electron-mobility transistor. The author has an hindex of 11, co-authored 24 publications receiving 275 citations.

A MODFET-based optoelectronic integrated circuit receiver for optical interconnects

Abstract: The design, fabrication, and characterization of a 0.85- mu m sensitive photoreceiver is described. The monolithically integrated optoelectronic receiver is based on pseudomorphic InGaAs on GaAs modulation-doped field-effect transistors (MODFETs) and metal-semiconductor-metal (MSM) photodetectors. High-performance quarter-micrometer MODFETs with f/sub t/'s of approximately 70 GHz are utilized in a two-stage transimpedance amplifier. An asymmetric and a symmetric amplifier design are compared. The symmetric design is found to provide the desired zero DC offset voltage for a variety of supply voltages. Excess MSM-detector dark current and low-frequency internal gain are greatly reduced through the use of a silicon passivation layer and/or AlGaAs cap layer. Receiver transimpedances between 100 and 5000 Omega are obtained by varying the bias on an active feedback resistor. The parasitic capacitances of this common-gate feedback FET are studied. A transimpedance amplifier bandwidth as high as 14 GHz and an overall photoreceiver bandwidth of 11 GHz are measured. >

InAlAs/InGaAs/InP MODFET's with uniform threshold voltage obtained by selective wet gate recess

Abstract: Excellent uniformity in the threshold voltage, transconductance, and current-gain cutoff frequency of InAlAs/InGaAs/InP MODFETs has been achieved using a selective wet gate recess process. An etch rate ratio of 25 was achieved for InGaAs over InAlAs using a 1:1 citric acid:H/sub 2/O/sub 2/ solution. By using this solution for gate recessing, the authors have achieved a threshold voltage standard deviation of 15 mV and a transconductance standard deviation of 15 mS/mm for devices across a quarter of a 2-in-diameter wafer. The average threshold voltage, transconductance, and current-gain cutoff frequency of 1.0- mu m gate-length devices were -234 mV, 355 mS/mm, and 32 GHz, respectively. >

Selective Wet Etching Characteristics of Lattice‐Matched InGaAs / InAlAs / InP

Abstract: A selectivity study of the etching of lattice-matched InGaAs, and InAlAs, and InP in citric acid H/ 2 O 2 solutions is reported. Selectivities as high as 500 and 187 are obtained for the etching of InGaAs in InP and InAlAs on InP, respectively. The selectivity for the etching of InGaAs on InAlAs varies from 25 at a citric acid/H 2 O 2 solution ratio of 1 to selectivity of 2.5 at a solution ratio of 10

InAlAs/InGaAs heterostructure FET's processed with selective reactive-ion-etching gate-recess technology

Abstract: A highly selective reactive-ion-etching process based on HBr plasma has been used as a gate-recess technique in fabrication of InAlAs/InGaAs heterostructure FETs. A typical 0.75- mu m-gate-length transistor exhibited a threshold voltage of -1.0 V, a maximum extrinsic transconductance of 600 mS/mm, an extrinsic current-gain cutoff frequency of 37 GHz, and a maximum frequency of oscillation of 90 GHz. These DC and RF device parameters compare favorably with those of a corresponding device gate-recessed with a selective wet-etching technique. >

Process for enhancement/depletion-mode GaAs/InGaAs/AlGaAs pseudomorphic MODFETs using selective wet gate recessing

Abstract: A process for enhancement/depletion (E/D)-mode GaAs/InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors (MODFETs) using citric acid: H2O2 solutions for selective wet gate recessing has been developed. Extrinsic DC transconductances gm as high as 450 and 600 mS/mm, and unity current-gain cutoff frequencies ft of 75 and 66 GHz at room temperature have been achieved for 0.3 μm gate-length depletion-mode MODFET (DFET) and enhancement-mode MODFET (EFET), respectively. Standard deviations for threshold voltage and transconductance of less than 16 mV and 25 mS/mm, respectively, have been achieved for both the DFETs and EFETs. Ring oscillators fabricated in direct-coupled FET logic technology have exhibited a propagation delay of 13 ps at room temperature.

Short-Channel Effect Limitations on High-Frequency Operation of AlGaN/GaN HEMTs for T-Gate Devices

Abstract: AlGaN/GaN high-electron mobility transistors (HEMTs) were fabricated on SiC substrates with epitaxial layers grown by multiple suppliers and methods. Devices with gate lengths varying from 0.50 to 0.09 mum were fabricated on each sample. We demonstrate the impact of varying the gate lengths and show that the unity current gain frequency response (fT) is limited by short-channel effects for all samples measured. We present an empirically based physical model that can predict the expected extrinsic fT for many combinations of gate length and commonly used barrier layer thickness (tbar) on silicon nitride passivated T-gated AlGaN/GaN HEMTs. The result is that even typical high-aspect-ratio (gate length to barrier thickness) devices show device performance limitations due to short-channel effects. We present the design tradeoffs and show the parameter space required to achieve optimal frequency performance for GaN technology. These design rules differ from the traditional GaAs technology by requiring a significantly higher aspect ratio to mitigate the short-channel effects.

Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap

Abstract: Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic transceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology.

Fully embedded board-level guided-wave optoelectronic interconnects

Abstract: A fully embedded board-level guided-wave optical interconnection is presented to solve the packaging compatibility problem. All elements involved in providing high-speed optical communications within one board are demonstrated. Experimental results on a 12-channel linear array of thin-film polyimide waveguides, vertical-cavity surface-emitting lasers (VCSELs) (42 /spl mu/m), and silicon MSM photodetectors (10 /spl mu/m) suitable for a fully embedded implementation are provided. Two types of waveguide couplers, titled gratings and 45/spl deg/ total internal reflection mirrors, are fabricated within the polyimide waveguides. Thirty-five to near 100% coupling efficiencies are experimentally confirmed. By doing so, all the real estate of the PC board surface are occupied by electronics, and therefore one only observes the performance enhancement due to the employment of optical interconnection but does not worry about the interface problem between electronic and optoelectronic components unlike conventional approaches. A high speed 1-48 optical clock signal distribution network for Cray T-90 super computer is demonstrated. A waveguide propagation loss of 0.21 dB/cm at 850 nm was experimentally confirmed for the 1-48 clock signal distribution and for point-to-point interconnects. The feasibility of using polyimide as the interlayer dielectric material to form hybrid three-dimensional interconnects is also demonstrated. Finally, a waveguide bus architecture is presented, which provides a realistic bidirectional broadcasting transmission of optical signals. Such a structure is equivalent to such IEEE standard bus protocols as VME bus and FutureBus.

Focal-plane-arrays and CMOS readout techniques of infrared imaging systems

Abstract: A discussion of CMOS readout technologies for infrared (IR) imaging systems is presented. First, the description of various types of IR detector materials and structures is given. The advances of detector fabrication technology and microelectronics process technology have led to the development of large format array of IR imaging detectors. For such large IR FPAs which is the critical component of the advanced infrared imaging system, general requirement and specifications are described. To support a good interface between the FPA and downstream signal processing stage, both conventional and CMOS readout techniques are presented and discussed. Finally, future development directions including the smart focal plane concept are also introduced.