K. Raghunathan

Bio: K. Raghunathan is an academic researcher from Binghamton University. The author has contributed to research in topics: Flip chip & Ball grid array. The author has an hindex of 1, co-authored 1 publications receiving 38 citations.

Predictive Model for Optimized Design Parameters in Flip-Chip Packages and Assemblies

Abstract: An analytical model is developed to predict the out-of- plane deformation and thermal stresses in multilayered thin stacks subjected to temperature. Coefficient of thermal expansion mismatches among the components (chip, substrate, underfill, flip-chip interconnect or C4s) are the driving force for both first and second levels interconnect reliability concerns. Die cracking and underfill delamination are the concerns for the first level interconnects while the ball grid array solder failure is the primary concern for the second level interconnects. Inadvertently, many researchers use the so-called rule of mixture in its effective moduli for the flip chip solder (C4)/underfill layer. In this study, a proper formula for effective moduli of solder (C4)/underfill layer, is presented. The classical lamination theory is used to predict the out-of-plane displacement of the chip substrate structure under temperature variation (DeltaT). The warpage and stresses resulting from the analytical formulation are compared with the 3-D finite element analysis. The study helps to design more reliable components or assemblies with the design parameters being optimized in the early stage of the development using closed form analytical solutions.

Warpage Analysis of Flip-Chip PBGA Packages Subject to Thermal Loading

Abstract: The aim of this paper was to measure and simulate the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260?C). In the experiments, a full-field shadow moirE? was used to measure real-time out-of-plane deformations (warpages) on the substrate and chip surfaces of the flip-chip packages under thermal heating and cooling conditions. A finite-element method (FEM) and Suhir's die-assembly theory, together with the measured material data (elastic moduli and coefficients of thermal expansion (CTEs) for organic substrates), were used to analyze the thermally induced deformations of the packages to gain insight into their mechanics. The strain gauge data used to determine the CTEs of the substrates also indicated that there was nearly no bending strain under thermal loading. The full-field warpages on the substrate surface of the packages from the shadow moirE? were documented under temperature loading. It was also found that there were different zero-warpage temperatures (which resulted in a variation of warpages at room temperature) for the four test packages during thermal loading, but they had similar warpage rates (the slope of warpage with respect to temperature). This might have been due to the creep of the underfill and the solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be well simulated or predicted by FEM and Suhir's theory. The key material properties (elastic moduli and CTEs for the substrate and underfill) that affect the maximum warpage of the package were thoroughly studied. It was found that, among these material properties, a low elastic modulus for the underfill can significantly reduce the maximum warpage, while its CTE is much less sensitive to warpage. Moreover, the substrate CTE affects the warpage of a package only with noncompliant underfills, while a typical substrate elastic modulus (ranging from 10 to 30 GPa) is insensitive to warpage, unless its value is lower than a few gigapascals.

Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

Abstract: 2.5D packages have been widely used in electronics industry for high performance and product miniaturization. As Through-Silicon-Via (TSV) fabrication methods and multi-level assembly technologies get mature, 2.5D packaging becomes reliable and affordable. In this work, board-level life prediction was performed for a 2.5D Field-Programmable Gate Array (FPGA) assembly in both accelerated thermal cycling and power cycling. Finite element models were built and validated by warpage measurement. Solder fatigue life in power cycling was investigated by computational fluid dynamics (CFD) simulation and finite element analysis. Improved life prediction for power cycling was achieved by mapping temperature results from CFD model to finite element model. Parametric studies regarding geometry and material factors were performed including PCB, substrate, thermal interface material (TIM) and lid adhesive, to give design suggestions to improve board-level thermal reliability. Maximum junction temperature of a 2.5D FPGA package is dependent on application scenarios and working environment. It is found that the designed maximum junction temperature and applied heatsink clamping force have considerable influences on board-level reliability.

A Study of Hygrothermal Behavior of ACF Flip Chip Packages With Moiré Interferometry

Abstract: A primary factor of anisotropic conductive film (ACF) package failure is delamination between the chip and the adhesive at the edge of the chip. This delamination is mainly affected by the thermal shear strain at the edge of the chip. This shear strain was measured on various electronic ACF package specimens by micro-Moire interferometry with a phase shifting method. In order to find the effect of moisture, the reliability performance of an adhesive flip-chip in the moisture environment was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical contact. Different geometric size specimens in terms of interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between the adhesive and other components in the package, which induces hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated by using the Moire interferometry. From Moire measurement results, we could also obtain the stress intensity factor K. Through an analysis of deformations induced by thermal and moisture environments, a damage model for an adhesive flip-chip package is proposed.