K. Takeuchi

Bio: K. Takeuchi is an academic researcher. The author has contributed to research in topics: Statistical model. The author has an hindex of 1, co-authored 1 publications receiving 34 citations.

Statistical Compact Model Parameter Extraction by Direct Fitting to Variations

Abstract: In this paper, a new method of statistical compact model parameter extraction is proposed and described in detail. The method is characterized in that the target of fitting is not the individual transistor, but statistically analyzed results (more specifically, principal components) of measured data. Variations of transistor characteristics can be translated into equivalent variations of compact model parameters by only one fitting step without repeating the parameter extraction procedure multiple times. Since the fitting is based on the response of a compact model to parameters, detailed information of the model is not necessary. The method has been applied to modeling the variations of metal-oxide-semiconductor field-effect transistor current versus voltage characteristics, and its validity has been confirmed.

Analog-to-Digital Conversion

Abstract: The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for every new design. Analog-to-Digital Conversion discusses the different analog-to-digital conversion principles: sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation. Analog-to-Digital Conversion presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed while reducing the power level. A lot of background knowledge and practical tips complement the discussion of basic principles, which makes Analog-to-Digital Conversion also a reference for the experienced engineer.

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

Abstract: The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.

Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies

Abstract: The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current) when subjected to fin roughness up to 1 nm root-mean-square amplitude. Spacer-defined FinFETs show negligible device performance variation and exhibit quadratic dependence with LER amplitude. For both patterning technologies, the resulting impact on large-scale digital-circuit performance variation is found to be minimal in terms of the overall delay mean and variation. This is attributed to self-averaging of uncorrelated LER effects between individual devices within the circuits, resulting in minimal delay impact for digital-circuit design. The impact of LER on leakage power variation is also found to be minimal for all technologies; however, the mean value increases by up to 40% for 15-nm resist FinFETs. On this basis, the impact of LER on sub-32-nm FinFET device-level variability is only significant for resist devices, whereas the resulting digital-circuit impact is important only in terms of mean leakage power increase.

Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies

Abstract: In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits From a device-level perspective, JL FinFETs are severely impacted by process variations: up to 40% and 60% fluctuation in threshold voltage is observed from LER RDF Conversely, results show that variability-induced shifts and broadening of timing and power in large-scale digital circuits are not significant and can be accommodated in the design budget However, we find that LER has a large impact on static noise margin analysis of 6T SRAMs Required Vccmin values for SRAMs using JL devices reach up to 2× those implemented in conventional IM technologies The yield for JL SRAM is completely compromised in the presence of realistic levels of LER and RDF Fortunately, the impact of variability is somewhat reduced with scaling for JL designs; both LER and RDF induce less variation for the 15-nm node compared with the 32-nm node The observed reduction in Vccmin with technology scaling suggests that digital circuits implemented with JL FinFETs may eventually offer the same level of operability as those based on IM FinFETs, especially in the presence of circuit-level SRAM robustness optimizations

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

Abstract: In this paper, we present a FinFET-focused variability-aware compact model (CM) extraction and generation technology supporting design-technology co-optimization. The 14-nm CMOS technology generation silicon on insulator FinFETs are used as testbed transistors to illustrate our approach. The TCAD simulations include a long-range process-induced variability using a design of experiment approach and short-range purely statistical variability (mismatch). The CM extraction supports a hierarchical CM approach, including nominal CM extraction, response surface CM extraction, and statistical CM extraction. The accurate CM generation technology captures the often non-Gaussian distributions of the key transistor figures of merit and their correlations preserving also the correlations between process and statistical variability. The use of the hierarchical CM is illustrated in the simulation of FinFET-based SRAM cells and ring oscillators.