K.Y. Lim

Bio: K.Y. Lim is an academic researcher from Chartered Semiconductor Manufacturing. The author has contributed to research in topics: Ring oscillator & Low voltage. The author has an hindex of 1, co-authored 1 publications receiving 66 citations.

32nm general purpose bulk CMOS technology for high performance applications at low voltage

Abstract: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.

Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study

Abstract: It has recently become clear that the use of high-κ /metal gate stacks will have a distinct impact on the intrinsic parameter variability of the corresponding CMOS devices. The metal gates have a natural granularity, with the work function of each grain depending on its orientation. Here, we present a full-scale 3-D statistical simulation study of the statistical variability induced by this metal gate granularity (MGG). We investigate the effect of grain size on both the magnitude of the variability and the shape of the corresponding statistical distribution. The distributions in threshold voltage due to MGG are analyzed in isolation and in combination with random discrete dopants and line-edge roughness.

The BubbleWrap many-core: popping cores for sequential acceleration

Abstract: Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, many of the cores may have to be dormant at any given time to meet the power budget. To push back the many-core power wall, this paper proposes Dynamic Voltage Scaling for Aging Management (DVSAM) --- a new scheme for managing processor aging to attain higher performance or lower power consumption. In addition, this paper introduces the BubbleWrap many-core, a novel architecture that makes extensive use of DVSAM. BubbleWrap identifies the most power-efficient set of cores in a variation-affected chip --- the largest set that can be simultaneously powered-on --- and designates them as Throughput cores dedicated to parallel-section execution. The rest of the cores are designated as Expendable and are dedicated to accelerating sequential sections. BubbleWrap attains maximum sequential acceleration by sacrificing Expendable cores one at a time, running them at elevated supply voltage for a significantly shorter service life each, until they completely wear-out and are discarded --- figuratively, as if popping bubbles in bubble wrap that protects Throughput cores. In simulated 32-core chips, BubbleWrap provides substantial improvements over a plain chip. For example, on average, one design runs fully-sequential applications at a 16% higher frequency, and fully-parallel ones with a 30% higher throughput.

CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

Abstract: Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed.

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

Abstract: The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

Abstract: Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.