An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Numerical analyses on optimizing a heat pipe thermal management system for lithium-ion batteries during fast charging

Because heterogeneous materials can be designed to
exhibit the best characteristics of their individual
constituents, they are ideally suited to modern
technologies that require materials with an unusual
combination of properties. The study presented in
the current work is aimed to approach effective
electrical conductivity of various random
heterogeneous materials. It starts with the
description of a type of modern material with
specific morphology. Percolation theory and finite
element analysis are used in computations and
comparison with experimental results is provided. To
understand difficulties with classical approaches,
next a two-component composite material on a lattice
is studied, followed by discoveries in the
electrical field properties. Finally, a new
algorithm is suggested, which can be used to find
effective properties for any arbitrary morphology.
Material covered in this book will be of interest to
graduate students and researchers who work on the
front edge of physics, materials science,
engineering and applied mathematics. All necessary
derivations and definitions are included to make the
book self-contained and approachable.

Random Heterogeneous Materials

A sealable module, cooled electronic system and method are described relating to cooling a heat generating electronic device. The sealable module is adapted to be filled with a first cooling liquid and a heat transfer device having a conduction surface defines a channel for receiving a second cooling liquid. In one embodiment, at least a portion of the conduction surface or housing is shaped in conformity with the shape of the electronic component. Control of the second cooling liquid is also described. Transferring heat between the second cooling liquid and a third cooling liquid features in embodiments. A method of filling a container with a cooling liquid is further detailed.

Cooled electronic system

Air cooled heat sink geometries subjected to forced flow: A critical review

The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material (e.g., thermal paste), wherein a thermal interface is designed to prevent/inhibit the formation of voids in the compliant thermally conductive material due to the flow of such material in and out from between the chips and the heat conducting device due to thermal cycling.

Apparatus and Methods for Cooling Semiconductor Integrated Circuit Package Structures

Disclosed is a cooling structure which has individual spreaders or caps mounted on the chips. The thickness of the high power spreader or cap exceeds the thickness of the lower power spreaders to ensure that the high power spreader achieves the highest plane and mates to a heat sink with the smallest interface gap. The variable and higher gaps between the lower power spreaders and the heat sink base are accommodated by compressible thermal pad or grease materials.

Method and structure for cooling a dual chip module with one high power chip

A method and apparatus for electronic chip assembly maintains a thin gap spacing between the chip and the lid or heat sink and provides for the electronic chip to operate at a relatively cool temperature. The thermal performance is enhanced by a thermal interface material provided in the thin gap and maintained at a minimal thickness as a result of the structure and assembly process. A thin thermal interface material layer may be achieved with a compression step to compress the thermal interface material before the sealant is cured. In addition, a vent hole is provided in the assembly to prevent pressure build-up inside the module during sealant cure. As the sealant is cured, the gap spacing is maintained, further compression of the thermal interface material is not required, and seal defects are prevented.

Method for controlling thermal interface gap distance

An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.

Segmentation of a die stack for 3d packaging thermal management

A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate.

Kamal K. Sikka

Papers

Apparatus and Methods for Cooling Semiconductor Integrated Circuit Package Structures

Method and structure for cooling a dual chip module with one high power chip

Method for controlling thermal interface gap distance

Segmentation of a die stack for 3d packaging thermal management

Enhanced thermal management of 3-D stacked die packaging