Showing papers by "Kamaljit Rangra published in 2014"

Design of novel compact anti-stiction and low insertion loss RF MEMS switch

Abstract: A novel torsional RF MEMS capacitive switch design on silicon substrate is presented. The optimized switch topology such as reduction in up-state capacitance results in insertion loss better than ź0.1 dB till 20 GHz. Off to on state capacitance ratio is also improved by 18 fold and isolation is better than ź43 dB at 9.5 GHz. The achieved on state return loss is ź38 dB as compared to ź21 dB at 9.5 GHz. An optimized reduction in contact area and use of floating metal layer increases the switching speed from 56 to 46 μsec. It also increases the switch reliability by alleviating the stiction.

Comparative study of various release methods for gold surface micromachining

Abstract: A comparison of dry and wet release methods for surface micromachining of metallic structures, such as RF MEMS switches, test structures, bridges, and cantilevers is presented. The dry release process is opti- mized by varying the concentration of O2 and CF4 plasma and RF power. The plasma ashing of the sacrificial layer typically results in damage to metallic structures or stress-related deformation due to rise in temperature (>80°C). A wet release process using critical point drying (CPD) has been investigated to realize gold-electro- plated structures with reduced residual stress. The CPD, being a low-temperature (31.1°C) process, is more suitable for compliant structures without any deformation. © 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)

A novel interdigitated, inductively tuned, capacitive shunt RF — MEMS switch for X and K bands applications

Abstract: This paper presents a new type of capacitive shunt RF-MEMS switch. In the proposed design, interdigitation of signal lines with actuation electrodes is used to make a compact device. A bridge structure anchored in between ground planes and attached to two cantilevers on either side has been used to implement the switch structure. This novel structure is used to inductively tune the isolation peaks in X and K bands which is not possible with conventional approach. The designed switch shows an insertion loss of 0.01 dB to 0.11 dB over the frequency range from 1 to 25 GHz. Isolation of 34.71, 34.33, and 40.7 dB has been observed at 10.4 GHz, 11 GHz and 21.4 GHz when bridge is electro-statically actuated with either left, right or both cantilevers in the down state respectively. The bridge structure shows a pull-in voltage of 12.25 V and switching time of 34.40 μs whereas left and right cantilevers have 7.5 V and 57 μs. The designed device can be useful for the future multiband communication applications.

Residual stress control during the growth and release process in gold suspended microstructures

Abstract: This paper presents the growth and release process effects on the deformation of suspended gold micro-structures. Cantilever type test structures, typically used for RF MEMS devices have been examined. The structures have a thickness of 2μm, produced by patterned gold electro deposition above a sacrificial photoresist layer, then removed by dry release in oxygen plasma ashing and wet release using critical point dryer (CPD). The growth process of gold electroplating is optimized for low residual stress using pulse power supply. Minimum stress 35-60 MPa is obtained at grain size 30-45nm and RMS roughness of the order of 5-8nm. The growth mechanism of structural layer and releasing methods are optimized to obtain planar MEMS structures. The main parameters considered are the initial stress during the growth of electroplated gold and the release process recipes developed for fabrication of metallic structural layer.

Low cost process for development of electrostatically actuated optical devices using gold electroplating

Abstract: This paper presents a low cost fabrication process for development of electrostatically actuated optical microstructures. To illustrate the process - a design, fabrication and measurement iteration for digital micromirror test structures is presented. The structures are fabricated on Single Crystal Silicon wafer using surface micromachining and gold electroplating. The major focus of the work has been on the process compatibility with conventional CMOS fabrication technology, lower cost, complexity, lower surface roughness and susceptibility of compliant structures to thermal cycling during the process. Thelstructures consist of 1–2 micron thick micromirrors suspended at a height of 2–5 micron and surface roughness of 22–30 nm. Vertical deflection (3 micron), pull-in voltage (31V) and mechanical resonance frequency (25 KHz) match within 5–10% to the simulated design. The approach can be extended to realize optical switches, light modulators, grating structures, barcode readers and optical scanners.