This paper introduces a new topology of multilevel inverter, which is able to operate at high performance This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility In most cases fifteen-level inverters need at least twelve switches The proposed topology has only ten switches The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms The detailed operation of the proposed inverter is explained The theoretical analysis and design procedure are given Simulation results are presented to confirm the analytical approach of the proposed circuit A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz

https://ijpeds.iaescore.com/index.php/IJPEDS/article/download/20738/13268

A high-performance multilevel inverter with reduced power electronic devices

This study presents a performance assessment of a single photovoltaic (PV) array fed transformer-based five-level converter topology with optimal shift factor-based modified sinusoidal pulse width modulation (OSF-MSPWM) technique under a dynamic solar PV environment. The five-level converter output is generated using H bridge cells and single-phase transformers. A single PV array is fed to all cascaded H bridge cells and isolation is provided by cascading secondary windings of the transformers in the AC side. The separate DC sources requirement is eliminated and galvanic isolation is provided by single-phase transformers. The decoupled controller with modified in-phase disposition PWM technique is used for active power injection into the grid at unity power factor. This work uses a new carrier shape at the same input carrier frequency and modulation index m f for improving the harmonics performance of the five-level converter. Hence, shift the dominant harmonics to the higher side for developed topology and performing optimal shift factor-based modulation is compared with the conventional SPWM technique. The steady-state and dynamic responses of the PV multilevel converter are observed in MATLAB simulation and tested in a real-time platform.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-pel.2020.0438

Modified spwm technique for improved harmonic performance of single pv array fed grid-tied five-level converter

Pulse Width Modulation (PWM) methods are used to control the switching sequence operations of conventional Multilevel Inverter (MLI) and Reduced Switch Multilevel Inverters (RSMLI). Many researchers proposed various RSMLIs with their switching sequence operation and PWM control techniques. But, the switching operations of RSMLIs are not similar to conventional MLIs which are major problem of switch control. Logical equations are proposed for the operation of RSMLIs with the multi carrier pulse width modulation methods like, Alternative Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) and Phase Disposition (PD). To operate the individual switch in RSMLI, logical operators are used to produce required pulse sequence from the sequence of PWM method and their analysis is not present in previous works. The proposed methodology and binary representation of PWM method are analyzed on various RSMLIs for 7 level output voltage. Control of individual switching sequence and the operation of RSMLIs are simulated using MATLAB/Simulink. THD comparison is presented for RSMLIs with various PWM methods.

/pdf/analysis-of-switching-sequence-operation-for-reduced-switch-1erpkhye6r.pdf

Analysis of Switching Sequence Operation for Reduced Switch Multilevel Inverter With Various Pulse Width Modulation Methods

Reduction of switch count in symmetrical and asymmetrical reduced switch multilevel inverter designs has been proposed regularly with operation of conventional carrier-based pulse width modulation technique. In this study, a novel structure of symmetrical Hexa shaped model reduced switch seven level output inverter is proposed without any auxiliary switch and H-bridge. Proposed structure offers a smaller number of switch count and voltage sources which results in the cost and complexity reduction of its implementation. To operate the switching sequence of inverter from carrier based APOD, POD and PD methods, suitable logical expression to be realize which gained more prominence. Active utilization of two voltage sources in each mode of operation results in significant reduction of voltage stress across each switch is achieved. A comparative study of proposed MLI with various reduced switch MLIs has been presented. Initially, simulation model implementation has been carried out with MATLAB/Simulink and observed the performance parameters and THD. Simulation results are carried for the comparison of the results obtained in the real time work performed on OPAL-RT 5700 simulator .

https://ijpeds.iaescore.com/index.php/IJPEDS/article/download/21227/13576

Real time simulation of reduced switch multilevel inverter with PWM switching sequence control

Introduction. In recent years the usage of electricity has increased tremendously as the electrical needs and loads got increased. Hence the researchers focused on the electricity generation from renewable sources in order to promote sustainable green environment. Owing to the lesser cost and more reliable high efficiency system with reduced use of equipments became prominent for the grid connected photovoltaic single phase systems. The novelty of this proposed converters are to reduce total power loss and to analyze the performance of the converter under various modulation index and to have lesser harmonics using sinusoidal pulse width modulation technique for both T-type and F-type inverter. Interest of the work is to merge two DC-DC converters which have same output voltage in order to have transformer less utilization of power. This has given pathway to develop a new DC-DC converter network by merging the common input nodes of CUK and SEPIC converter. Purpose. This similar structure of both converters made it easy to combine the input stages of and to get bipolar output. Methods. Here we can get bipolar output without the utilization of transformer which minimizes the overall size of the proposed system. In this paper, a combined CUK-SEPIC based grid connected transformerless inverter for photovoltaic application is suggested. Results. The suggested converter is simulated using MATLAB and the results were discussed. Further the circuit is extended with a 1 kW F-type inverter to demonstrate grid connection of the converter. Practical value. This converter can be implemented for photovoltaic applications for obtaining the bipolar DC output from the DC source.

/pdf/bipolar-dc-output-fed-grounded-dc-ac-converter-for-23rxojk9.pdf

Bipolar DC output fed grounded DC-AC converter for photovoltaic application

Analysis of logic gates for the switching sequence operation of reduced switch multilevel inverter (MLI) is introduced in this paper. Two variants of MLI with reduced switches are considered for the analysis of the logic gates to obtain proper output voltage level. One MLI is with the symmetrical voltage, and the other is with the asymmetrical voltage. The analysis of the proposed logical operation is presented through the single-phase seven-level output voltage for both symmetrical and asymmetrical inverters. Input pulse pattern for the operation of the logic gates are chosen from the multi carrier pulse width modulation (PWM) techniques as phase disposition (PD), phase opposition disposition (POD), and alternate POD (APOD). The analysis for the generation of the required pulse pattern to operate the switches in MLI is presented as logical equations. The simulation work is performed and evaluated with the MATLAB/Simulink. The real-time simulation is performed for the required pulse pattern and generated with the support of dSPACE 1104. The THD comparative analysis is analyzed with a modulation index and various PWM methods.

/pdf/analysis-of-logic-gates-for-generation-of-switching-sequence-4suu6e7y3r.pdf

Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter

Requirement of power saving is essential for the present scenario. Conventional Multilevel Inverters (MLI) are having more switches, but they have wide range of attractive applications with effective results. The research article presents a novel structure of reduced switch single phase seven level multilevel inverter. Each DC source in the proposed structure is integrated with DC boost converter. Therefore, the proposed structure ensures the less switching losses, reduced size and cost of the structure. Comparative study of proposed MLI and conventional cascaded MLI is presented with various logical analyses of pulse width modulation (PWM) methods. The performance analysis in terms of THD is presented with the comparison of cascaded MLI and proposed MLI. Simulation design and validation of the comparative analysis is carried with MATLAB/SIMULINK.

Kanike Vinod Kumar

Papers

Analysis of Logic Gates for Generation of Switching Sequence in Symmetric and Asymmetric Reduced Switch Multilevel Inverter

Real time simulation of reduced switch multilevel inverter with PWM switching sequence control

Structure of Boost DC and Multilevel Inverter with Reduced Switches for 7 level

Optimizing Agricultural to Hydro power water transfer