In complementary metal–oxide–semiconductor (CMOS) logic circuits, the main design requirement for low-power applications is to reduce the power dissipation. Dynamic power dissipation occurs in clock network which contributes up to 30–45% of total power dissipation of circuit mostly because of flip-flop are being used for sequencing which consumes lot of power therefore to reduce the power consumption flip-flop are being replaced with pulsed latch circuit with feedback. Conditional circuit is used in bidirectional shift register with bidirectional pulsed latch circuit. When it is compared with master–slave flip-flop, power reduction is 38%. Modified circuit is being implemented in 28 nm CMOS technology.

Karan Kumar

Papers

Power-Efficient Bidirectional Shift Register Using Conditional Bidirectional Pulsed Latch Circuit