Karim El Khadiri

Bio: Karim El Khadiri is an academic researcher from Sidi Mohamed Ben Abdellah University. The author has contributed to research in topics: CMOS & Voltage. The author has an hindex of 3, co-authored 34 publications receiving 43 citations. Previous affiliations of Karim El Khadiri include SIDI.

A low noise, high PSR low-dropout regulator for low-cost portable electronics

Abstract: This paper presents A low noise, high PSRR low-dropout regulator for low-cost portable electronics The proposed LDO uses an Operational Transconductance Amplifier (OTA) with Miller R-C compensation to ensure a stable phase margin greater than 62° The active chip of the proposed regulator is only 150×680 um2 The design was simulated and lyouted in Cadence using mixed-signal 90 nm 2P9M CMOS process, the simulation results show that this LDO output voltage can achieves line regulation of less than 010% and load regulation of better than 025% and a low quiescent current of only 90uA and ultra-low noise of only 65 nV/SqrtHz Moreover, it can achieve a PSRR of -52 dB and -64 dB at 1 and 10 kHz, respectively The input voltage is ranged from 270 to 5 V for a load current 100 mA and an output voltage of 15 V

Integrated energy management converter based on maximum power point tracking for photovoltaic solar system

Abstract: This paper presents an integrated power control system for photovoltaic systems based on maximum power point tracking (MPPT). The architecture presented in this paper is designed to extract more power from photovoltaic panels under different partial obscuring conditions. To control the MPPT block, the integrated system used the ripple correlation control algorithm (RCC), as well as a high-efficiency synchronous direct current (DC-DC) boost power converter. Using 180 nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed MPPT was designed, simulated, and layout in virtuoso cadence. The system is attached to a two-cell in series that generates a 5.2 V average output voltage, 656.6 mA average output current, and power efficiency of 95%. The final design occupies only 1.68 mm2.

New Analog Li-Ion Battery Charger Using Pulsed Charging Method

Abstract: This paper presents a new analog Li-Ion battery charger using pulsed charging. Simple structure, low cost and small size, the proposed analog battery charger is a very low cost solution because it doesn't need any calibration and no precise external resistor is needed to end of charge detection. This charger is implemented in TSMC 0.18um CMOS process with a power supply equal to 5V. The maximum charging current reaches 800mA with output voltage over or equal to 4.2V. The layout occupies a small active area of 1.5 mm2, the power dissipation is about 837mW and high-power efficiency of 92%.

Li-Ion Battery Charger Based on LDO Regulator for Portable Device Power Management

Abstract: This paper presents an architecture of a charger based on an LDO regulator with high efficiency for a Li-Ion battery which controlled the three-mode: trickle current, fast constant current and constant voltage modes. The simulation results provide the trickle current of 250mA, maximum charging current of 1. 12A and charging voltage of 4. 2V at the power supply of 4.8-5V using TSMC 180nm CMOS technology.

Thwarting analog IC piracy via combinational locking

Abstract: With a relatively small number of components, analog ICs are much more vulnerable to piracy, and especially reverse engineering, than many digital ICs. However, analog IC security has received much less research attention than digital ICs. We introduce a combinational locking technique using configurable current mirror for analog IC protection. The locking circuit is designed by applying Satisfiability Modulo Theories. With the locking system, only a single key value can make analog IC operate properly while the other key values result in significant performance degradation or malfunction. Moreover, circuit output is not monotone function with respect to key values and thus systematic attack is difficult to be effective. Experimental results demonstrate that this technique can largely thwart analog IC piracy with limited overhead.

A Review on Hot-Carrier-Induced Degradation of Lateral DMOS Transistor

Abstract: With the scaling of process node and increase of operation voltage, the electrical fields and impact ionization generation rates in lateral double-diffused MOS (LDMOS) transistors are obviously increased. As a result, a detailed characterization and understanding for long-term hot-carrier-induced (HCI) effect of LDMOS have been becoming more and more important. This review compares and summarizes the HCI damage locations and degradation mechanisms for all kinds of typical LDMOS devices under different stress conditions. Finally, generalized conclusions on HCI effect of LDMOS are deduced, and some special degradation influence factors brought by the device design technologies are also clarified.

How Multi-Threshold Designs Can Protect Analog IPs

Abstract: Analog Integrated Circuits (ICs) are one of the top targets for counterfeiting. However, the security of analog Intellectual Property (IP) is not well investigated as its digital counterpart. In this paper, we explore the possibility of multi-threshold voltage (VTH) design to protect the analog IP from Reverse Engineering (RE)-based attacks. Analog circuits are sensitive to VTH as the operating region of a transistor can vary with VTH. Furthermore, the VTH of individual transistors cannot be identified during the RE process. The trial-and-error based technique to guess the VTH and validate with a golden IC will ramp up RE effort exponentially. Thus, by carefully including multi-VTH transistors, the designer can ensure that the properties of analog IP e.g., gain, bandwidth, and linearity are protected even though the physical dimensions of the transistors are revealed. We demonstrate this technique by using a case study on a wide-swing cascode amplifier. Simulations show that incorrect VTH inference can lead to substantially degraded performance like 98 dB drop in open-loop gain and up to 19% increase in total harmonic distortion. Based on VTH choice, the proposed technique can save ~ 3% area over conventional design. We show that the reverse engineering effort can be ~1013 years. We propose a technique like transistor splitting to increase the effort even more. Mismatch analysis shows that the proposed technique results in only 1% loss in mean robustness.

Modeling and simulation of photovoltaic module for space applications using Simulink/MATLAB

Abstract: This paper presents an enhanced model of photovoltaic (PV) module for space application. The model is represented by two diodes equivalent circuit for each single junction and implemented in Simulink / MATLAB. It is validated using real requirements of space mission with real space PV cell characteristics. The fundamental equations of the PV cell are utilized with the influences of space radiation and the variation of the operating temperature. The P-V and I-V characteristics as a function of space radiation and the operating temperature are presented. The comparison of the modeling results with the published data from the manufacturer shows a satisfactory accuracy with max error 5.9 % for the whole voltage range. The model is used to implement a complete space photovoltaic system for space applications. Finally, the model is used to compare the performance of single crystal Si module and multi-junction module using a real mission requirement of a satellite platform.