Departing from traditional communication theory where decoding algorithms are assumed to perform without error, a system where noise perturbs both computational devices and communication channels is considered here. This paper studies limits in processing noisy signals with noisy circuits by investigating the effect of noise on standard iterative decoders for low-density parity-check (LDPC) codes. Concentration of decoding performance around its average is shown to hold when noise is introduced into message-passing and local computation. Density evolution equations for simple faulty iterative decoders are derived. In one model, computing nonlinear estimation thresholds shows that performance degrades smoothly as decoder noise increases, but arbitrarily small probability of error is not achievable. Probability of error may be driven to zero in another system model; the decoding threshold again decreases smoothly with decoder noise. As an application of the methods developed, an achievability result for reliable memory systems constructed from unreliable components is provided.

Performance of LDPC Codes Under Faulty Iterative Decoding

http://www.ece.ualberta.ca/~jhan8/publications/PGM_Proof_onLine.pdf?origin=publication_detail

Reliability evaluation of logic circuits using probabilistic gate models

Conventional communications theory assumes that the data transmission is noisy but the processing at the receiver is entirely error-free. Such assumptions may have to be revisited for advanced (silicon) technologies in which hardware failures are a major concern at the system-level. Hence, it is important to characterize the performance of a communication system with both noisy processing components and noisy data transmission. Coding systems based on low-density parity check (LDPC) codes are widely used for a variety of applications. In this paper, we focus on probabilistic analysis of the LDPC Gallager B decoder built out of faulty components. Using the density evolution technique, we find approximations for the optimal threshold of the decoder and the symbol error rate (SER) of the decoded sequence as functions of both the channel error rate and error rates of the decoder components, for both binary and non-binary regular LDPC codes. Furthermore, we study the convergence of the output SER and the decoding threshold of the decoder for different ranges of error rates. We verify our results using MATLAB simulations and hardware emulation of noisy decoders. Results presented in this paper can serve as systematic design guidelines in resource allocation for noisy decoders. Informed resource allocation is of particular relevance to emerging data storage and processing applications that need to maintain high levels of reliability despite hardware errors in advanced technologies.

Gallager B Decoder on Noisy Hardware

In nano-domain logic circuits, errors generated are transient in nature and will arise due to the uncertainty or the unreliability of the computing element itself. This type of errors - which we refer to as dynamic errors - are to be distinguished from traditional faults and radiation related errors. Due to these highly likely dynamic errors, it is more appropriate to model nano-domain computing as probabilistic rather than deterministic. We propose a probabilistic error model based on Bayesian networks to estimate this expected output error probability, given dynamic error probabilities in each device since this estimate is crucial for nano-domain circuit designers to be able to compare and rank designs based on the expected output error. We estimate the overall output error probability by comparing the outputs of a dynamic error-encoded model with an ideal logic model. We prove that this probabilistic framework is a compact and minimal representation of the overall effect of dynamic errors in a circuit. We use both exact and approximate Bayesian inference schemes for propagation of probabilities. The exact inference shows better time performance than the state-of-the art by exploiting conditional independencies exhibited in the underlying probabilistic framework. However, exact inference is worst case NP-hard and can handle only small circuits. Hence, we use two approximate inference schemes for medium size benchmarks. We demonstrate the efficiency and accuracy of these approximate inference schemes by comparing estimated results with logic simulation results. We have performed our experiments on LGSynth'93 and ISCAS'85 benchmark circuits. We explore our probabilistic model to calculate: 1) error sensitivity of individual gates in a circuit; 2) compute overall exact error probabilities for small circuits; 3) compute approximate error probabilities for medium sized benchmarks using two stochastic sampling schemes; 4) compare and vet design with respect to dynamic errors; 5) characterize the input space for desired output characteristics by utilizing the unique backtracking capability of Bayesian networks (inverse problem); and 6) to apply selective redundancy to highly sensitive nodes for error tolerant designs.

/pdf/probabilistic-error-modeling-for-nano-domain-logic-circuits-4qg2p4h441.pdf

Probabilistic Error Modeling for Nano-Domain Logic Circuits

With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, we propose probabilistic macromodels for standard QCA circuit elements based on conditional probability characterization, defined over the output states given the input states. Any circuit model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate three uses for these macromodel-based circuits. First, the probabilistic macromodels allow us to model the logical function of QCA circuits at an abstract level - the "circuit" level - above the current practice of layout level in a time and space efficient manner. We show that the circuit level model is orders of magnitude faster and requires less space than layout level models, making the design and testing of large QCA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Second, the probabilistic macromodels abstract crucial device level characteristics such as polarization and low-energy error state configurations at the circuit level. We demonstrate how this macromodel-based circuit level representation can be used to infer the ground state probabilities, i.e., cell polarizations, a crucial QCA parameter. This allows us to study the thermal behavior of QCA circuits at a higher level of abstraction. Third, we demonstrate the use of these macromodels for error analysis. We show that low-energy state configurations of the macromodel circuit match those of the layout level, thus allowing us to isolate weak points in circuits design at the circuit level itself

/pdf/hierarchical-probabilistic-macromodeling-for-qca-circuits-556b3y1whp.pdf

Hierarchical Probabilistic Macromodeling for QCA Circuits

We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a dynamic Bayesian network. Dynamic Bayesian networks are extremely powerful in modeling high order temporal as well as spatial correlations; it is an exact model for the underlying conditional independencies. The attractive feature of this graphical representation of the joint probability function is that not only does it make the dependency relationships amongst the nodes explicit but it also serves as a computational mechanism for probabilistic inference. We report average errors in switching probability of 0.006, with errors tightly distributed around the mean error values, on IS-CAS'89 benchmark circuits involving up to 10000 signals.

/pdf/estimation-of-switching-activity-in-sequential-circuits-1bi1eu4ji6.pdf

Estimation of switching activity in sequential circuits using dynamic

/pdf/estimation-of-switching-activity-in-sequential-circuits-4b7134xl7s.pdf

Estimation of switching activity in sequential circuits using dynamic Bayesian networks

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits

Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS Such devices would have inherent propensity for gate failures due to the underlying device variabilities Many of these failures would be transient in nature, necessitating the need for probabilistic logic base danalysis Current research in this area is concerned with computing error bounds, but they do not account for circuits structures or are usually derived for specific logic gate types In addition, the usual focus is on computing the average error behavior In this work, we propose an exact probabilistic error model to compute the maximum error in a circuit-specific manner and can handle various types of logical components in the same circuit We model the error estimation problem as a maximum a posteriori estimate (MAP) over the joint error probability function of the entire circuit Using this model, we can not only compute the maximum error, but can also identify the input vector that cause the maximum output error We demonstrate this model using MCNC and ISCAS circuits We observe that for some circuits, maximum error probabilities are significantly larger than the average likelihood error, thus making acase for the consideration of maximum error metric as an essential design guideline rather than just average-case estimates We also find that the error estimates depend on the specific circuit structure Lastly, we observe that the maximum error probabilities are sensitive to the individual gate failure probabilities

/pdf/probabilistic-maximum-error-modeling-for-unreliable-logic-1trqm84t84.pdf

Karthikeyan Lingasubramanian

Papers

Probabilistic Error Modeling for Nano-Domain Logic Circuits

Estimation of switching activity in sequential circuits using dynamic

Estimation of switching activity in sequential circuits using dynamic Bayesian networks

Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits

Probabilistic maximum error modeling for unreliable logic circuits