Kathleen Philips

TL;DR: The fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW and the energy efficiency of this converter can be maintained down to very low sampling rates.

TL;DR: In this paper, a design method for the co-design and integration of a CMOS rectifier and small loop antenna and a complementary MOS diode is proposed to improve the harvester's ability to store and hold energy over a long period of time during which there is insufficient power for rectification.

TL;DR: An ultra-low power single chip transceiver for wireless body area network (WBAN) applications that supports on-off keying (OOK) modulation, and it is integrated in an electrocardiogram (ECG) necklace to monitor the heart's electrical property.

TL;DR: This work presents a 2.1-to-2.7GHz 860μW fractional-N ADPLL in 40nm CMOS for WPAN applications, which breaks the 1mW barrier and consumes at least 5× lower power compared to state-of-the-artADPLLs.

TL;DR: This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a /spl Sigma//spl Delta/ ADC, which becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel.