Kathryn W. Guarini

TL;DR: A simple, robust, chemical route to the fabrication of ultrahigh-density arrays of nanopores with high aspect ratios using the equilibrium self-assembled morphology of asymmetric diblock copolymers is shown.

TL;DR: This work demonstrates the smallest 6T and full 8T-SRAM cells to date and provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling.

TL;DR: Target applications including surface-roughening for on-chip decoupling capacitors, patterning nanocrystal floating gates for FLASH devices, and defining FET channel arrays are discussed.

TL;DR: In this article, a self-organizing diblock copolymer system with semiconductor processing is combined to produce silicon capacitors with increased charge storage capacity over planar structures.

TL;DR: In this paper, a novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFETs on (100) surface) through wafer bonding and selective epitaxy devices with physical gate oxide thickness of 12 nm.