Katsuhiro Tomioka

Bio: Katsuhiro Tomioka is an academic researcher from Hokkaido University. The author has contributed to research in topics: Nanowire & Epitaxy. The author has an hindex of 28, co-authored 102 publications receiving 3737 citations. Previous affiliations of Katsuhiro Tomioka include Gunma University & National Presto Industries.

A III–V nanowire channel on silicon for high-performance vertical transistors

Abstract: The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

GaAs/AlGaAs Core Multishell Nanowire-Based Light-Emitting Diodes on Si

Abstract: We report on integration of GaAs nanowire-based light-emitting-diodes (NW-LEDs) on Si substrate by selective-area metalorganic vapor phase epitaxy. The vertically aligned GaAs/AlGaAs core-multishell nanowires with radial p-n junction and NW-LED array were directly fabricated on Si. The threshold current for electroluminescence (EL) was 0.5 mA (current density was approximately 0.4 A/cm2), and the EL intensity superlinearly increased with increasing current injections indicating superluminescence behavior. The technology described in this letter could help open new possibilities for monolithic- and on-chip integration of III−V NWs on Si.

Control of InAs Nanowire Growth Directions on Si

Abstract: We report on control of growth directions of InAs nanowires on Si substrate. We achieved to integrate vertical InAs nanowires on Si by modifying initial Si(111) surface in selective-area metal-organic vapor phase epitaxy with flow-rate modulation mode at low temperature. Cross-sectional transmission electron microscope and Raman scattering showed that misfit dislocation with local strains were accommodated in the interface.

Growth of Core–Shell InP Nanowires for Photovoltaic Application by Selective-Area Metal Organic Vapor Phase Epitaxy

Abstract: We report on the formation of core–shell pn junction InP nanowires using a catalyst-free selective-area metalorganic vapor-phase epitaxy (SA-MOVPE) method. A periodically aligned dense core–shell InP nanowire array was fabricated and used in photovoltaic device applications. The device exhibited open-circuit voltage (VOC), short-circuit current (ISC) and fill factor (FF) levels of 0.43 V, 13.72 mA/cm2 and 0.57, respectively, which indicated a solar power conversion efficiency of 3.37% under AM1.5G illumination. This study demonstrates that high quality core–shell structure nanowire fabrication is possible by SA-MOVPE and that the nanowire arrays can be used in integrated nanowire photovoltaic devices.

III–V Nanowires on Si Substrate: Selective-Area Growth and Device Applications

Abstract: III-V nanowires (NWs) on Si are promising building blocks for future nanoscale electrical and optical devices on Si platforms. We present position-controlled and orientation-controlled growth of InAs, GaAs, and InGaAs NWs on Si by selective-area growth, and discuss how to control growth directions of III-V NW on Si. Basic studies on III-V/Si interface showing heteroepitaxial growth with misfit dislocations and coherent growth without misfit dislocations are presented. Finally, we demonstrate the integrations of a III-V NW-based vertical surrounding-gate field-effect transistor and light-emitting diodes array on Si. These demonstrations could have broad applications in high-electron-mobility transistors, laser diodes, and photodiodes with a functionality not enabled by conventional NW devices.

Electronics based on two-dimensional materials

Abstract: The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Tunnel field-effect transistors as energy-efficient electronic switches

Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Light-emitting diodes

Abstract: Light-Emitting Diodes. (Monographs in Electrical and Electronic Engineering.) By A. A. Bergh and P. J. Dean. Pp. viii+591. (Clarendon: Oxford; Oxford University: London, 1976.) £22.

A review of Ga2O3 materials, processing, and devices

Abstract: Gallium oxide (Ga2O3) is emerging as a viable candidate for certain classes of power electronics, solar blind UV photodetectors, solar cells, and sensors with capabilities beyond existing technologies due to its large bandgap. It is usually reported that there are five different polymorphs of Ga2O3, namely, the monoclinic (β-Ga2O3), rhombohedral (α), defective spinel (γ), cubic (δ), or orthorhombic (e) structures. Of these, the β-polymorph is the stable form under normal conditions and has been the most widely studied and utilized. Since melt growth techniques can be used to grow bulk crystals of β-GaO3, the cost of producing larger area, uniform substrates is potentially lower compared to the vapor growth techniques used to manufacture bulk crystals of GaN and SiC. The performance of technologically important high voltage rectifiers and enhancement-mode Metal-Oxide Field Effect Transistors benefit from the larger critical electric field of β-Ga2O3 relative to either SiC or GaN. However, the absence of clear demonstrations of p-type doping in Ga2O3, which may be a fundamental issue resulting from the band structure, makes it very difficult to simultaneously achieve low turn-on voltages and ultra-high breakdown. The purpose of this review is to summarize recent advances in the growth, processing, and device performance of the most widely studied polymorph, β-Ga2O3. The role of defects and impurities on the transport and optical properties of bulk, epitaxial, and nanostructures material, the difficulty in p-type doping, and the development of processing techniques like etching, contact formation, dielectrics for gate formation, and passivation are discussed. Areas where continued development is needed to fully exploit the properties of Ga2O3 are identified.

InP Nanowire Array Solar Cells Achieving 13.8% Efficiency by Exceeding the Ray Optics Limit

Abstract: Photovoltaics based on nanowire arrays could reduce cost and materials consumption compared with planar devices but have exhibited low efficiency of light absorption and carrier collection. We fabricated a variety of millimeter-sized arrays of p-type/intrinsic/n-type (p-i-n) doped InP nanowires and found that the nanowire diameter and the length of the top n-segment were critical for cell performance. Efficiencies up to 13.8% (comparable to the record planar InP cell) were achieved by using resonant light trapping in 180-nanometer-diameter nanowires that only covered 12% of the surface. The share of sunlight converted into photocurrent (71%) was six times the limit in a simple ray optics description. Furthermore, the highest open-circuit voltage of 0.906 volt exceeds that of its planar counterpart, despite about 30 times higher surface-to-volume ratio of the nanowire cell.