K
Katsuya Okumura
Researcher at Tokyo Electron
Publications - 311
Citations - 3023
Katsuya Okumura is an academic researcher from Tokyo Electron. The author has contributed to research in topics: Substrate (printing) & Electrode. The author has an hindex of 28, co-authored 311 publications receiving 3008 citations. Previous affiliations of Katsuya Okumura include Kyocera & Sumitomo Electric Industries.
Papers
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Journal ArticleDOI
Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method
TL;DR: In this article, the authors demonstrate the feasibility of ultrahigh-density bumpless interconnect by realizing the ultrafine pitch bonding of Cu electrodes at room temperature by using surface-activated bonding (SAB) method.
Journal ArticleDOI
10–15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing
Takayuki Ito,Toshihiko Iinuma,Atsushi Murakoshi,Haruko Akutsu,Kyoichi Suguro,Tsunetoshi Arikado,Katsuya Okumura,Masaki Yoshioka,Tatsushi Owada,Yasuhiro Imaoka,Hiromi Murayama,Tatsuhumi Kusuda +11 more
TL;DR: Flash-lamp annealing (FLA) as mentioned in this paper is a new method of activating implanted impurities, which is able to reduce the time of the heating cycle to within the millisecond range.
Patent
Multi-chip semiconductor device chip for multi-chip semiconductor device and its formation
TL;DR: In this article, the problem of providing a multi-chip semiconductor device whose device area is small, whose constitution is simple and whose thickness is thin by providing a connection plug formed of metal in a through hole passing through a semiconductor substrate and an inter-layer insulating film and electrically connecting one chip with the other chip through the connection plug was addressed.
Patent
Chemical mechanical method of polishing wafer surfaces
Hiroyuki Yano,Gaku Minamihaba,Yukiteru Matsui,Hayasaka Nobuo,Katsuya Okumura,Akira Iio,Masayuki Hattori,Masayuki Motonari +7 more
TL;DR: In this article, an aqueous dispersion and CMP slurry that can achieve polishing at an adequate rate without producing scratches in the polishing surfaces of wafer working films, and a polishing process for wafer surfaces and a process for manufacture of a semiconductor device using them.
Patent
Semiconductor wafer, device for manufacturing semiconductor device, method of manufacturing the semiconductor device, and method of manufacturing the semiconductor wafer
Tsunetoshi Arikado,Masao Iwase,Hiroshi Matsushita,Moriya Miyashita,Soichi Nadahara,Hajime Nagano,Shinichi Nitta,Katsuya Okumura,Jiyunji Sugamoto,Katsujiro Tanzawa,Norihiko Tsuchiya,Sukemune Udo,Yukihiro Ushiku,Yamada Korei,勝二郎 丹沢,憲彦 土屋,勝弥 奥村,守也 宮下,浩玲 山田,政雄 岩瀬,伸一 新田,祐宗 有働,経敏 有門,宏 松下,元 永野,壮一 灘原,幸広 牛久,淳二 菅元 +27 more
TL;DR: In this article, the authors propose a method of manufacturing a semiconductor device in which optimum process conditions in each manufacturing process can be adopted at high speed for each wafer, and a new product is formed on the wafer based on information indicated on the ID mark.