Kaustav Banerjee

Bio: Kaustav Banerjee is an academic researcher from University of California, Santa Barbara. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 64, co-authored 288 publications receiving 18170 citations. Previous affiliations of Kaustav Banerjee include University of California, Berkeley & Stanford University.

Electrical contacts to two-dimensional semiconductors

Abstract: The performance of electronic and optoelectronic devices based on two-dimensional layered crystals, including graphene, semiconductors of the transition metal dichalcogenide family such as molybdenum disulphide (MoS2) and tungsten diselenide (WSe2), as well as other emerging two-dimensional semiconductors such as atomically thin black phosphorus, is significantly affected by the electrical contacts that connect these materials with external circuitry. Here, we present a comprehensive treatment of the physics of such interfaces at the contact region and discuss recent progress towards realizing optimal contacts for two-dimensional materials. We also discuss the requirements that must be fulfilled to realize efficient spin injection in transition metal dichalcogenides.

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Abstract: Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Role of metal contacts in designing high-performance monolayer n-type WSe2 field effect transistors.

Abstract: This work presents a systematic study toward the design and first demonstration of high-performance n-type monolayer tungsten diselenide (WSe2) field effect transistors (FET) by selecting the contact metal based on understanding the physics of contact between metal and monolayer WSe2. Device measurements supported by ab initio density functional theory (DFT) calculations indicate that the d-orbitals of the contact metal play a key role in forming low resistance ohmic contacts with monolayer WSe2. On the basis of this understanding, indium (In) leads to small ohmic contact resistance with WSe2 and consequently, back-gated In–WSe2 FETs attained a record ON-current of 210 μA/μm, which is the highest value achieved in any monolayer transition-metal dichalcogenide- (TMD) based FET to date. An electron mobility of 142 cm2/V·s (with an ON/OFF current ratio exceeding 106) is also achieved with In–WSe2 FETs at room temperature. This is the highest electron mobility reported for any back gated monolayer TMD materia...

MoS2 Field-Effect Transistor for Next-Generation Label-Free Biosensors

Abstract: Biosensors based on field-effect transistors (FETs) have attracted much attention, as they offer rapid, inexpensive, and label-free detection. While the low sensitivity of FET biosensors based on bulk 3D structures has been overcome by using 1D structures (nanotubes/nanowires), the latter face severe fabrication challenges, impairing their practical applications. In this paper, we introduce and demonstrate FET biosensors based on molybdenum disulfide (MoS2), which provides extremely high sensitivity and at the same time offers easy patternability and device fabrication, due to its 2D atomically layered structure. A MoS2-based pH sensor achieving sensitivity as high as 713 for a pH change by 1 unit along with efficient operation over a wide pH range (3–9) is demonstrated. Ultrasensitive and specific protein sensing is also achieved with a sensitivity of 196 even at 100 femtomolar concentration. While graphene is also a 2D material, we show here that it cannot compete with a MoS2-based FET biosensor, which ...

A subthermionic tunnel field-effect transistor with an atomically thin channel.

Abstract: A new type of device, the band-to-band tunnel transistor, which has atomically thin molybdenum disulfide as the active channel, operates in a fundamentally different way from a conventional silicon (MOSFET) transistor; it has turn-on characteristics and low-power operation that are better than those of state-of-the-art MOSFETs or any tunnelling transistor reported so far. Traditional transistor technology is fast approaching its fundamental limits, and two-dimensional semiconducting materials such as molybdenum disulfide (MoS2) are seen as possible replacements for silicon in a next generation of high-density, lower-power chip electronics. A particularly promising prospect is their potential in band-to-band tunnel transistors, which operate in a fundamentally different way from conventional silicon (MOSFET) transistors. So far, few such devices with overall characteristics better than silicon transistors have been demonstrated. Now Kaustav Banerjee et al. have built a tunnel transistor by making a vertical structure with atomically thin MoS2 as the active channel and germanium as the source electrode. It has turn-on characteristics and low-power operation that are better than those of existing silicon transistors, and the results will be of interest in a range of electronic applications including low-power integrated circuits, as well as ultra-sensitive bio sensors or gas sensors. The fast growth of information technology has been sustained by continuous scaling down of the silicon-based metal–oxide field-effect transistor. However, such technology faces two major challenges to further scaling. First, the device electrostatics (the ability of the transistor’s gate electrode to control its channel potential) are degraded when the channel length is decreased, using conventional bulk materials such as silicon as the channel. Recently, two-dimensional semiconducting materials1,2,3,4,5,6,7 have emerged as promising candidates to replace silicon, as they can maintain excellent device electrostatics even at much reduced channel lengths. The second, more severe, challenge is that the supply voltage can no longer be scaled down by the same factor as the transistor dimensions because of the fundamental thermionic limitation of the steepness of turn-on characteristics, or subthreshold swing8,9. To enable scaling to continue without a power penalty, a different transistor mechanism is required to obtain subthermionic subthreshold swing, such as band-to-band tunnelling10,11,12,13,14,15,16. Here we demonstrate band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on; subthreshold swing is a minimum of 3.9 millivolts per decade and an average of 31.1 millivolts per decade for four decades of drain current at room temperature. By using highly doped germanium as the source and atomically thin molybdenum disulfide as the channel, a vertical heterostructure is built with excellent electrostatics, a strain-free heterointerface, a low tunnelling barrier, and a large tunnelling area. Our atomically thin and layered semiconducting-channel tunnel-FET (ATLAS-TFET) is the only planar architecture tunnel-FET to achieve subthermionic subthreshold swing over four decades of drain current, as recommended in ref. 17, and is also the only tunnel-FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts. Our device is at present the thinnest-channel subthermionic transistor, and has the potential to open up new avenues for ultra-dense and low-power integrated circuits, as well as for ultra-sensitive biosensors and gas sensors18,19,20,21.

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Abstract: 抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

Phd by thesis

Abstract: Deposits of clastic carbonate-dominated (calciclastic) sedimentary slope systems in the rock record have been identified mostly as linearly-consistent carbonate apron deposits, even though most ancient clastic carbonate slope deposits fit the submarine fan systems better. Calciclastic submarine fans are consequently rarely described and are poorly understood. Subsequently, very little is known especially in mud-dominated calciclastic submarine fan systems. Presented in this study are a sedimentological core and petrographic characterisation of samples from eleven boreholes from the Lower Carboniferous of Bowland Basin (Northwest England) that reveals a >250 m thick calciturbidite complex deposited in a calciclastic submarine fan setting. Seven facies are recognised from core and thin section characterisation and are grouped into three carbonate turbidite sequences. They include: 1) Calciturbidites, comprising mostly of highto low-density, wavy-laminated bioclast-rich facies; 2) low-density densite mudstones which are characterised by planar laminated and unlaminated muddominated facies; and 3) Calcidebrites which are muddy or hyper-concentrated debrisflow deposits occurring as poorly-sorted, chaotic, mud-supported floatstones. These

Ultrasensitive photodetectors based on monolayer MoS2.

Abstract: A very sensitive photodector based on molybdenum disulphide with potential for integrated optoelectronic circuits, light sensing, biomedical imaging, video recording or spectroscopy is now demonstrated.

Recent Advances in Ultrathin Two-Dimensional Nanomaterials

Abstract: Since the discovery of mechanically exfoliated graphene in 2004, research on ultrathin two-dimensional (2D) nanomaterials has grown exponentially in the fields of condensed matter physics, material science, chemistry, and nanotechnology. Highlighting their compelling physical, chemical, electronic, and optical properties, as well as their various potential applications, in this Review, we summarize the state-of-art progress on the ultrathin 2D nanomaterials with a particular emphasis on their recent advances. First, we introduce the unique advances on ultrathin 2D nanomaterials, followed by the description of their composition and crystal structures. The assortments of their synthetic methods are then summarized, including insights on their advantages and limitations, alongside some recommendations on suitable characterization techniques. We also discuss in detail the utilization of these ultrathin 2D nanomaterials for wide ranges of potential applications among the electronics/optoelectronics, electrocat...

Nanoscale thermal transport

Abstract: Rapid progress in the synthesis and processing of materials with structure on nanometer length scales has created a demand for greater scientific understanding of thermal transport in nanoscale devices, individual nanostructures, and nanostructured materials. This review emphasizes developments in experiment, theory, and computation that have occurred in the past ten years and summarizes the present status of the field. Interfaces between materials become increasingly important on small length scales. The thermal conductance of many solid–solid interfaces have been studied experimentally but the range of observed interface properties is much smaller than predicted by simple theory. Classical molecular dynamics simulations are emerging as a powerful tool for calculations of thermal conductance and phonon scattering, and may provide for a lively interplay of experiment and theory in the near term. Fundamental issues remain concerning the correct definitions of temperature in nonequilibrium nanoscale systems. Modern Si microelectronics are now firmly in the nanoscale regime—experiments have demonstrated that the close proximity of interfaces and the extremely small volume of heat dissipation strongly modifies thermal transport, thereby aggravating problems of thermal management. Microelectronic devices are too large to yield to atomic-level simulation in the foreseeable future and, therefore, calculations of thermal transport must rely on solutions of the Boltzmann transport equation; microscopic phonon scattering rates needed for predictive models are, even for Si, poorly known. Low-dimensional nanostructures, such as carbon nanotubes, are predicted to have novel transport properties; the first quantitative experiments of the thermal conductivity of nanotubes have recently been achieved using microfabricated measurement systems. Nanoscale porosity decreases the permittivity of amorphous dielectrics but porosity also strongly decreases the thermal conductivity. The promise of improved thermoelectric materials and problems of thermal management of optoelectronic devices have stimulated extensive studies of semiconductor superlattices; agreement between experiment and theory is generally poor. Advances in measurement methods, e.g., the 3ω method, time-domain thermoreflectance, sources of coherent phonons, microfabricated test structures, and the scanning thermal microscope, are enabling new capabilities for nanoscale thermal metrology.