K
KC Sivaramakrishnan
Researcher at Indian Institute of Technology Madras
Publications - 33
Citations - 525
KC Sivaramakrishnan is an academic researcher from Indian Institute of Technology Madras. The author has contributed to research in topics: Concurrency & Asynchronous communication. The author has an hindex of 13, co-authored 31 publications receiving 405 citations. Previous affiliations of KC Sivaramakrishnan include University of Cambridge & Purdue University.
Papers
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Proceedings ArticleDOI
Declarative programming over eventually consistent data stores
TL;DR: QUELEA is presented, a declarative programming model for eventually consistent data stores (ECDS), equipped with a contract language, capable of specifying fine-grained application - level consistency properties, and an implementation of QUEleA on top of an off-the-shelf ECDS that provides support for coordination-free transactions.
Book ChapterDOI
Concurrent System Programming with Effect Handlers
Stephen K. Dolan,Spiros Eliopoulos,Daniel Hillerström,Anil Madhavapeddy,KC Sivaramakrishnan,Leo White +5 more
TL;DR: It is made the observation that effect handlers can elegantly express particularly difficult programs that combine system programming and concurrency without compromising performance.
Proceedings ArticleDOI
Bounding data races in space and time
TL;DR: This work proposes a new semantics for shared-memory parallel programs that gives strong guarantees even in the presence of data races, and provides a straightforward operational semantics and an equivalent axiomatic model for OCaml.
Journal ArticleDOI
Safe replication through bounded concurrency verification
TL;DR: A novel programming framework for replicated data types (RDTs) equipped with an automatic (bounded) verification technique that discovers and fixes weak consistency anomalies and shows that in practice, proving bounded safety guarantees typically generalize to the unbounded case.
Journal ArticleDOI
MultiMLton: A multicore-aware runtime for standard ML
TL;DR: The rationale, design, and implementation of MultiMLton are described, and experimental results over a range of parallel benchmarks and different multicore architectures including an 864 core Azul Vega 3, and a 48 core non-coherent Intel SCC (Single-Cloud Computer), that justify the design decisions are provided.